(Invited) Low Power Tunneling FET Technologies Using Ge/III-V Materials

Takagi, Shinichi; Ahn, Dae‐Hwan; Noguchi, M.; Yoon, Sang-Hee; Gotow, Takahiro; Nishi, Koichi; Kim, Min‐Soo; Bae, Tae-Eon; Katoh, Takeo; Matsumura, Ryo; Takaguchi, Ryotaro; Takenaka, Mitsuru

doi:10.1149/08004.0115ecst

Cited by 4 publications

(7 citation statements)

References 33 publications

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“…There are two different TFET structures. One is the typical pn-junction-based TFETs using InGaAs (13)(14)(15)(16)(17)(18)(19), InGaAs quantum well (15,16,(20)(21)(22), GaAsSb/ InGaAs (15,16,28,29), GaSb/InAs (15,16), Ge (30)(31)(32), Ge/Si (33)(34)(35)(36) and Ge/strained Si (32,34). The other structure is the bi-layer TFETs using ZnO/Si, SiGe and Ge hetero-interfaces (37).…”

Section: Present Approach To Tfets Using Iii-v Materialsmentioning

confidence: 99%

“…InGaAs with the sufficiently-low and direct bandgap is one of the most promising channel materials for n-TFETs (13)(14)(15)(16)(17)(18)(19)(20)(21)(22)(23)(38)(39)(40)(41). On the other hand, a difficult task is to realize the formation of the source junctions with defect-less and steep impurity profiles, as described in the previous section.…”

Section: Ingaas Quantum-well Tfetsmentioning

confidence: 99%

“…In this paper, we focus on the challenges and the critical issues of III-V-based TFETs. First, we summarize our approach to TFETs in terms of the materials and structures (13)(14)(15)(16). Among a variety of TFETs, the fabrication and the characterization of InGaAs (13)(14)(15)(16)(17)(18)(19) and InGaAs quantum well TFETs (15,16,(20)(21)(22) are mainly described.…”

Section: Introductionmentioning

confidence: 99%

“…First, we summarize our approach to TFETs in terms of the materials and structures (13)(14)(15)(16). Among a variety of TFETs, the fabrication and the characterization of InGaAs (13)(14)(15)(16)(17)(18)(19) and InGaAs quantum well TFETs (15,16,(20)(21)(22) are mainly described. Next, an InAs MOS interface control technology is introduced for aiming at realization of future InAs CMOS and complementary TFETs (23,24).…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

(Invited)Ultra-Low Power III-V-Based MOSFETs and Tunneling FETs

Takagi
¹
,

Ahn
²
,

Gotow
³

et al. 2018

ECS Trans.

2
0
2
0

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The technical challenges and viable technologies of tunneling MOSFETs (TFET) using III-V semiconductors are present in this paper. Device engineering indispensable in improving the performance of TFETs is summarized. In particular, the electrical characteristics of TFETs using In0.53Ga0.47As/higher-In-content InGaAs/In0.53Ga0.47As quantum well (QW) structures are addressed as viable examples. Also, the effect of surface pre-treatment on InAs on the MOS interface properties, important for the InAs MOSFET and TFET performance, is presented. In addition, the electrical properties of In0.53Ga0.47As MOSFETs using ALD La2O3 gate insulators with ferroelectric-like hysteresis are also introduced as another possible direction for steep slope devices.

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Section: Present Approach To Tfets Using Iii-v Materialsmentioning
confidence: 99%

Section: Ingaas Quantum-well Tfetsmentioning
confidence: 99%

Section: Introductionmentioning
confidence: 99%

See 2 more Smart Citations
(Invited)Ultra-Low Power III-V-Based MOSFETs and Tunneling FETs
Takagi
¹
,
Ahn
²
,
Gotow
³

et al. 2018
ECS Trans.
2
0
2
0
View full text Add to dashboard Cite
The technical challenges and viable technologies of tunneling MOSFETs (TFET) using III-V semiconductors are present in this paper. Device engineering indispensable in improving the performance of TFETs is summarized. In particular, the electrical characteristics of TFETs using In0.53Ga0.47As/higher-In-content InGaAs/In0.53Ga0.47As quantum well (QW) structures are addressed as viable examples. Also, the effect of surface pre-treatment on InAs on the MOS interface properties, important for the InAs MOSFET and TFET performance, is presented. In addition, the electrical properties of In0.53Ga0.47As MOSFETs using ALD La2O3 gate insulators with ferroelectric-like hysteresis are also introduced as another possible direction for steep slope devices.
show abstract

“…Furthermore, we fabricate Ge p-TFETs with source junctions formed by the diffusion of these dopants from SOG and evaluate their electrical properties. The published abstract 30) also dealt with such topics, although details about the large leakage current in the I d -V g characteristics of the Ge p-TFETs were not discussed. In this paper, more details about this large leakage current are discussed.…”

Section: Introductionmentioning
confidence: 99%

Ge p-channel tunneling FETs with steep phosphorus profile source junctions
Takaguchi
¹
,
Matsumura
²
,
Katoh
³

et al. 2018
Jpn. J. Appl. Phys.
Self Cite
13
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6
0
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The solid-phase diffusion processes of three n-type dopants, i.e., phosphorus (P), arsenic (As), and antimony (Sb), from spin-on-glass (SOG) into Ge are compared. We show that P diffusion can realize both the highest impurity concentration (>7 ' 10 19 cm %3 ) and the steepest impurity profile (>10 nm/dec) among the cases of the three n-type dopants because the diffusion coefficient is strongly dependent on the dopant concentration. As a result, we can conclude that P is the most suitable dopant for the source formation of Ge p-channel TFETs. Using this P diffusion, we fabricate Ge p-channel TFETs with high-P-concentration and steep-P-profile source junctions and demonstrate their operation. A high ON current of >1.7 µA/µm is obtained at room temperature. However, the subthreshold swing and ON current/OFF current ratio are degraded by any generation-recombination-related current component. At 150 K, SS min of >108 mV/dec and ON/OFF ratio of >3.5 ' 10 5 are obtained.

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Structural analysis and resistivity measurements of InAs and GaSb fins on 300 mm Si for vertical (T)FET
Mols
¹
,
Bogdanowicz
²
,
Favia
³

et al. 2019
Journal of Applied Physics
12
1
10
0
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We report on the uniform selective area growth of InAs and GaSb by metal-organic vapor phase epitaxy on a patterned shallow trench isolation SiO2/Si 300 mm template. High-quality InAs fins are realized via direct InAs nucleation on Si in the trenches. 60° interfacial misfit dislocation arrays formed along the {111} oriented InAs/Si interfaces accommodate most of the lattice mismatch such that threading dislocation generation from residual strain is minimized. GaSb grown on a thick GaAs buffer (partial filling of the trench) suffers from twin formation. The twin density is found to decrease with increasing growth temperature. To maximize the volume of low-defect density material inside the trench, the GaSb growth is initiated as close as possible to the trench bottom. Therefore, uniform high-quality GaSb fins are grown on a very thin low-temperature GaAs and the newly developed InAs seed in the V-groove. High-resolution x-ray diffraction reciprocal space maps show that the InAs and GaSb fins are nearly completely relaxed. The resistivity of undoped and n-doped InAs and undoped and p-doped GaSb fins is measured on as-grown material by micro-4-point-probe without the need for additional complicated device processing. The values are compared to those required for devices as presented in modeling papers. The result is encouraging for the ultra-large-scale integration of vertical nanowire III-V (tunnel) field-effect transistor on 300 mm Si.

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(Invited) Low Power Tunneling FET Technologies Using Ge/III-V Materials

Cited by 4 publications

References 33 publications

(Invited)Ultra-Low Power III-V-Based MOSFETs and Tunneling FETs

(Invited)Ultra-Low Power III-V-Based MOSFETs and Tunneling FETs

Ge p-channel tunneling FETs with steep phosphorus profile source junctions

Structural analysis and resistivity measurements of InAs and GaSb fins on 300 mm Si for vertical (T)FET

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