CMOS and tunneling FETs (TFETs) utilizing Ge-On-Insulator (GOI) channels on Si substrates are expected as the promising device options for low-power integrated systems. In this paper, we present viable device and process technologies of GOI MOSFETs and TFETs on the Si CMOS platform. High compressive strain, favorable in p-MOSFET applications, is introduced in GOI films by optimizing the Ge condensation process and initial substrate structures, which is one of the most promising technologies to form ultrathin-body GOI p-MOSFETs. Also, source engineering in Ge layers to realize improved tunnel junctions with steep impurity profiles is developed for Ge/GOI TFET applications. In addition, impacts of Ge-based type-II hetero-structures such as Ge/strained-Si and Ge/ZnO on the TFET performance are studied. The electrical characteristics of GOI MOSFETs and TFETs are presented and analyzed from the viewpoints of applied strain, source junction properties and device structures.

The critical issues, technical challenges and viable technologies of tunneling FETs (TFET) using III-V semiconductors and Ge are addressed in this paper. Device engineering indispensable in improving the performance of TFETs is summarized with emphasis on the source junction formation technology. The fabrication and the electrical characteristics of TFETs using InGaAs bulk and quantum well (QW) homo-junctions, GaAsSb/InGaAs type-II hetero-junctions, Ge homo junctions and Ge/strained SOI type-II hetero-junction are presented as viable examples.

Tunneling field-effect transistors (TFETs) attract much attention for use in realizing next-generation low-power processors. In particular, Ge-oninsulator (GOI) TFETs are expected to realize low power operation with a high on-current/off-current (I on /I off ) ratio, owing to their narrow bandgap. Here, to improve the performance of GOI-TFETs, a source junction with a high doping concentration and an abrupt impurity profile is essential. In this study, a snowplow effect of NiGe combined with low-energy BF 2+ implantation has been investigated to realize an abrupt p + /n Ge junction for GOI n-channel TFETs. By optimizing the Ni thickness to form NiGe (thickness: 4 nm), an abrupt junction with a B profile abruptness of >5 nm/dec has been realized with a high doping concentration of around 10 21 cm %3 . The operation of GOI n-TFETs with this source junction having the abrupt B profile has been demonstrated, and the improvement of TFET properties such as the I on /I off ratio from 311 to 743 and the subthreshold slope from 368 to 239 mV/dec has been observed. This junction formation technology is attractive for enhancing the TFET performance.

The solid-phase diffusion processes of three n-type dopants, i.e., phosphorus (P), arsenic (As), and antimony (Sb), from spin-on-glass (SOG) into Ge are compared. We show that P diffusion can realize both the highest impurity concentration (>7 ' 10 19 cm %3 ) and the steepest impurity profile (>10 nm/dec) among the cases of the three n-type dopants because the diffusion coefficient is strongly dependent on the dopant concentration. As a result, we can conclude that P is the most suitable dopant for the source formation of Ge p-channel TFETs. Using this P diffusion, we fabricate Ge p-channel TFETs with high-P-concentration and steep-P-profile source junctions and demonstrate their operation. A high ON current of >1.7 µA/µm is obtained at room temperature. However, the subthreshold swing and ON current/OFF current ratio are degraded by any generation-recombination-related current component. At 150 K, SS min of >108 mV/dec and ON/OFF ratio of >3.5 ' 10 5 are obtained.