(Invited) Simulation Study of High Voltage Vertical GaN Nanowire Field Effect Transistors

Sabui, Gourab; Zubialevich, Vitaly Z.; Pampili, Pietro; White, Mark H.; Parbrook, P. J.; McLaren, Mathew; Arredondo, Miryam; Shen, Z. John

doi:10.1149/08007.0069ecst

Cited by 6 publications

(3 citation statements)

References 23 publications

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“…However, for improving the device design and performance, several strategies can be proposed for the next transistor generations, e.g., decreasing the Si-doping concentration in the drift region, integrating vertical field-plate structure, and employing longer drift region. The low doped and longer space drift region will reduce the local electric field and thus the BV can be increased 20,29,52 .…”

Section: Resultsmentioning

confidence: 99%

“…In the last few years, several vertical electronic devices based on semiconductor NWs (e.g., Si and GaN) have been demonstrated with different types of transistors, and only a few of them concern about the direct device scaling behavior as affected by the modified number and diameter of NWs 26–28 . The diameter size and doping concentration of n-n-n or n-i-n GaN epitaxial NWs were reported to be able to determine the operation modes of the GaN FETs (normally-off or normally-on) 29,30 . The threshold voltage can be increased by inserting a p -channel inside the wire structure instead of n -channel 13,28,30 .…”

Section: Introductionmentioning

confidence: 99%

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Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah

Feng

Strempel

et al. 2019

Sci Rep

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This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p -channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage ( V th ) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al 2 O 3 ) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (Δ V th ) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah

Feng

Strempel

et al. 2019

Sci Rep

View full text Add to dashboard Cite

show abstract

“…Increasing the distance between gate and drain will allow much higher breakdown voltages, as a larger part of the potential difference drops in the depleted drift region. In [24], breakdown voltages above 650 V are predicted for NW FETs with a similar device structure, when choosing suitable doping and geometries that ensure depletion of the drift region.…”

Section: Breakdown Voltagementioning

confidence: 99%

Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel

Strempel

Römer

Feng

et al. 2020

Semicond. Sci. Technol.

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This paper demonstrates the first vertical field-effect transistor based on gallium nitride (GaN) fin structures with an inverted p-doped channel layer. A top-down hybrid etching approach combining inductively coupled plasma reactive ion etching and KOH-based wet etching was applied to fabricate regular fields of GaN fins with smooth a-plane sidewalls. The obtained morphologies are explained using a cavity step-flow model. A 3D processing scheme has been developed and evaluated via focussed ion beam cross-sections. The top-down approach allows the introduction of arbitrary doping profiles along the channel without regrowth, enabling the modulation of the channel properties and thus increasing the flexibility of the device concept. Here, a vertical npn-doping profile was used to achieve normally-off operation with an increased threshold voltage as high as 2.65 V. The p-doped region and the 3D gate wrapped around the sidewalls create a very narrow vertical electron channel close to the interface between dielectric and semiconductor, resulting in good electrostatic gate control, low leakage currents through the inner fin core and high sensitivity to the interface between GaN and gate oxide. Hydrodynamic transport simulations were carried out and show good agreement with the performed current–voltage and capacitance–voltage measurements. The simulation indicates a reduced channel mobility which we attribute to interface scattering being particularly relevant in narrow channels. We also demonstrate the existence of oxide and interface traps with an estimated sheet density of 3.2 × 1012 cm−2 related to the Al2O3 gate dielectric causing an increased subthreshold swing. Thus, improving the interface quality is essential to reach the full potential of the presented vertical 3D transistor concept.

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Thermal performance analysis of GaN nanowire and fin-shaped power transistors based on self-consistent electrothermal simulations

Kamrani

Feng

Frank

et al. 2018

Microelectronics Reliability

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(Invited) Simulation Study of High Voltage Vertical GaN Nanowire Field Effect Transistors

Cited by 6 publications

References 23 publications

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel

Thermal performance analysis of GaN nanowire and fin-shaped power transistors based on self-consistent electrothermal simulations

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