Is TSV-based 3D Integration Suitable for Inter-die Memory Repair?

Lefter, Mihai; Voicu, George; Taouil, Mottaqiallah; Enachescu, Marius; Hamdioui, Said; Cotöfană, Sorin

doi:10.7873/date.2013.259

Cited by 4 publications

(3 citation statements)

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“…Preliminary research results show the significant benefits of using this vertical direction [21,23,52]. However, TSVs need to scale by at least one order of magnitude to make such schemes viable [53]. Other research publications analyzed the impact of TSV redundancy schemes [54][55][56]; however, they typically come with a high area overhead.…”

Section: Oportunities and Challengesmentioning

confidence: 99%

Challenges and Solutions in Emerging Memory Testing

Vatajelu

Prinetto

Taouil

et al. 2019

IEEE Trans. Emerg. Topics Comput.

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International audienceThe research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed

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Section: Oportunities and Challengesmentioning

confidence: 99%

Challenges and Solutions in Emerging Memory Testing

Vatajelu

Prinetto

Taouil

et al. 2019

IEEE Trans. Emerg. Topics Comput.

Self Cite

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“…Many works have been proposed to enhance the repair capability for 3D ICs [7][8][9]. However, how to efficiently repair the failures after die stacking is seldom touched.…”

Section: B Repair Challenges For Stacked Drammentioning

confidence: 99%

“…There are already some works proposed to enhance the repair capability for 3D ICs. However, these works focus either on the repair of defective TSVs [7] or on inter-die redundancy sharing [8,9]. Actually, once the manufacturing process of DRAM becomes stable, a large percentage of spares that are equipped with laser fuses will likely be left unused after wafer level repair.…”

Section: Introductionmentioning

confidence: 99%

Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares

Sun

Xin

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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Three dimensional (3D) integration is promising to provide dramatic performance and energy efficiency improvement to 3D logic-DRAM integrated computing system, but also poses significant challenge to the yield and reliability. By leveraging logic-DRAM co-design, this paper exploits the cost efficient approach to repair 3D integration induced defective cells in stacked DRAM with unused spares. In particular, we propose to make the DRAM array open its redundancy to off-chip access by small architecture modification, and further design the defective address comparison and redundant address remapping with very efficient architecture on logic die to achieve the equivalent memory repair. Simulation results have demonstrated that the proposed repair technique for DRAM after die stacking is able to significantly alleviate the yield loss, with very low area and power consumption overhead and negligible timing penalty.

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