Lateral Superjunction Reduced Surface Field Structure for the Optimization of Breakdown and Conduction Characteristics in a High-Voltage Lateral Double Diffused Metal Oxide Field Effect Transistor

Abstract

Superjunction devices are reported to provide better high-voltage operation characteristics than conventional abrupt junction devices in silicon power applications. In this study, the superjunction reduced surface field (SJ-RESURF) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) is fabricated on a bulk silicon wafer to improve the operating characteristics of high-voltage devices. By introducing the p-type strips in the drift region, higher doping concentration of the drift region can be adopted to reduce the conduction resistance. The SJ-RESURF LDMOSFET with a specific on-resistance of 3.53 Ámm 2 , a breakdown voltage of 335 V and a drift length of 30 mm, is demonstrated; its turn onresistance is 25% better than that of the conventional structure. The turn-on resistance, breakdown behavior, device geometry, temperature, and charge balance mechanics of the SJ-RESURF LDMOSFET are examined herein.

The Avalanche-Mode Superjunction LED

“…This is achieved using the superjunction (SJ) assisted reduced surface-field (RESURF) concept [17]- [20]. Although the SJ concept has been used in Si power devices [21]- [23] to overcome the breakdown voltage (V BR ) versus on-resistance (R ON ) trade-off, it has not been used in light-emitting diodes (LEDs). The proposed avalanchemode SJ-LEDs are lateral multi-finger diodes.…”

Optimization of Lateral Superjunction Based on the Minimum Specific ON-Resistance

“…The devices in [4]- [7] and [9] have the similar N and L d values as those from (5) and realize the optimizations. However, the devices in [2], [8], [10], and [13] only have the similar L d , and the devices in [3], [11], [12], and [14] have longer L d and lower N compared with the optimized conditions. in this paper is much higher than that in the reference, e.g., is up to almost 2.5 times for the device with W of 1 μm [10], [12], [13].…”

“…2) With the similar L d only, indicating that the SAD effects have been suppressed effectively [2], [8], [10], [13]. 3) With both the longer L d and lower N, as given in [3], [11], [12], and [14]. The larger improvements of R ON may be observed in the last two cases because of two reasons: first, the optimized N (6) with the same W and H as those in the references, and the simulated design results in this paper are given as the filled round dots.…”

“…The optimization of the lateral SJ device mainly focuses on the design of V B , i.e., the suppression of the substrate-assisted depletion (SAD) effect, which can be alleviated by removing the silicon substrate [2], [8] or introducing the charge compensation [1], [3]- [7], [9]- [14]. To analyze this effect, the equivalent substrate (ES) model was proposed in [1] to give the optimized substrate conditions.…”

Progression of Superjunction Power MOSFET Devices

“…For the lateral SJ devices, however, the substrate assisted depletion (SAD) is the main obstacle, which causes the charge imbalance, and thus limits the performance of the SJ-LDMOS device. Attempted approaches of adjusting the p-n column width of SJ structure [14] or combining both SJ and RESURF concepts [15], or adding an n-buffer layer under the SJ structure [16] could make incremental improvement to the performance of the SJ-LDMOS device on the bulk silicon substrate. However, the SAD effect still could not be fully eliminated.…”