Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

Senthilpari, C.; Diwakar, K.; Munusamy, Kumar; Francisca, J. Sheela

doi:10.1016/j.jestch.2016.08.012

Cited by 5 publications

(5 citation statements)

References 18 publications

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“…The scalability of FA cells is investigated by extending the FAs up to 32‐bits using simple ripple carry adder (RCA) method (Figure 6). 24,25 While extending the FAs, no intermediate voltage level restoring buffers were used. The performance of each FA in a wide adder structure is expressed in Table 5.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

Hasan

Islam

Hossain

et al. 2021

Circuit Theory & Apps

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High‐speed XOR‐XNOR‐based hybrid full adder (FA) using a combination of three logic techniques (transmission gate [TG], conventional CMOS [CCMOS], pass transistor [PT]) is presented in this work. Performance analysis and validation of the FA design presented in this work have been realized with reference to 10 state‐of‐the‐art FAs. The scalability of the design has been tested by extending FA up to 32‐bits in ripple carry adder (RCA) style. It has been observed that only four existing FAs and the proposed FA could be scaled up to 32‐bits without including voltage restoration buffers in the internal stages. The proposed XOR‐XNOR‐based FA showed excellent performance metrics, both as a 1‐bit adder cell as well as in wide word length adder form. Hence, the proposed XOR‐XNOR‐based hybrid FA can serve as a better alternative to the existing FAs in digital arithmetic blocks of modern microprocessors.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

Hasan

Islam

Hossain

et al. 2021

Circuit Theory & Apps

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“…An error bit contains either an even or odd number of 1s. [13]. An even parity bit makes the total number of 1s even and odd parity bit makes the total number of odd.…”

Section: G Detection Circuitmentioning

confidence: 99%

“…Parity can be used with any number of bits. The total code transmitted including the even parity bit is 0, 0101BCD Code [13]. Then let assume that an error occurs in the third bit from the left (the 1 becomes a 0).…”

Section: G Detection Circuitmentioning

confidence: 99%

“…However, at a rate of many millions of arithmetic operations per-second, such an error probability in computations can lead to several bit-errors per second. Thus, this investigation examines the key method that can improve the robustness and accuracy of the arithmetic circuit [7]. The main objective of this paper is to improve the logic blocks for detecting and correcting errors at the basic arithmetic operation level.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

International Journal of Electronics and Telecommunications

Kavitha¹,

Hashim²,

Kamal³

2019

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This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.

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“…These factors include switching capacitance, transition activity, and short circuit currents. The relative importance of these performance aspects varies depending on the specific application, the type of circuit being implemented, and the design technique employed [1][2][3]. The computational complexity of the circuits and the wireless communications systems is related to the area, number of components in the circuit, and power that is consumed.…”

Section: Introductionmentioning

confidence: 99%

Performance Enhancing of Nano-scale Technologies in Nuclear Applications Using C-MOS and FS-GDI Hybrid Approach

Mahmoud,

El-Bendary,

Kasban

2024

Arab Journal of Nuclear Sciences and Applications

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Nano-scale technologies have gained significant attention in various industries, including the nuclear field, due to their unique properties and potential benefits such as miniaturization and improved performance, radiation-hardened electronics, sensors, and detectors. This paper studies the performance of the different Nano-scale technologies in electronic elements fabrication using the different Full Adder (FA) circuits with respect to different realizing methods. Four main parameters; delay time, consumed power, simplicity of hardware (number of transistors),and Power Delay Product (PDP) have been used for evaluating the different FA circuits efficiency in 45nm and 65 nm Nanotechnologies and utilizing the Complementary Pass-Transistor Logic (CPL), Complementary Metal-Oxide-Semiconductor (C-MOS), Full-Swing Gate Diffusion Input (FS-GDI) hybrid approaches. The experiments are carried out using a simulator package (Cadence Virtuoso) for 65nm nanotechnology. The results revealed the performance of the FA circuits at the lower Nano-scale performed better than the higher nanoscale. C-MOS approaches provide better improvement in the 45 nm technology compared to the 65 nm technology and the other realizing approaches.

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Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

Cited by 5 publications

References 18 publications

A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

International Journal of Electronics and Telecommunications

Performance Enhancing of Nano-scale Technologies in Nuclear Applications Using C-MOS and FS-GDI Hybrid Approach

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