Lifetime-sensitive modulo scheduling

Huff, Richard A.

doi:10.1145/155090.155115

Cited by 165 publications

(102 citation statements)

References 21 publications

Supporting

Mentioning

101

Contrasting

Order By: Relevance

“…In this section, we compare HRMS with three schedulers: an heuristic method that does not take into account register requirements (FRLC [28]), a lifetime sensitive heuristic method (Slack [12]) and a linear programming approach (SPILP [10]). …”

Section: Comparison With Other Scheduling Methodsmentioning

confidence: 99%

“…Modulo scheduling is a class of software pipelining algorithms that was proposed at the begining of last decade [24] and has been incorporated into some product compilers (e.g., [22], [7]). Besides, many research papers have recently appeared on this topic [11], [14], [26], [13], [29], [12], [27], [23], [30], [18].…”

Section: Introductionmentioning

confidence: 99%

“…The two most relevant heuristic approaches proposed in the literature that try to minimize both the II and the register pressure are: Slack Scheduling [12] and Stage Scheduling [8].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Modulo scheduling with reduced register pressure

Llosa

Valero

Agyuade

et al. 1998

IEEE Trans. Comput.

View full text Add to dashboard Cite

Abstract-Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Modulo scheduling refers to a class of algorithms for software pipelining. Most previous research on modulo scheduling has focused on reducing the number of cycles between the initiation of consecutive iterations (which is termed II) but has not considered the effect of the register pressure of the produced schedules. The register pressure increases as the instruction level parallelism increases. When the register requirements of a schedule are higher than the available number of registers, the loop must be rescheduled perhaps with a higher II. Therefore, the register pressure has an important impact on the performance of a schedule. This paper presents a novel heuristic modulo scheduling strategy that tries to generate schedules with the lowest II, and, from all the possible schedules with such II, it tries to select that with the lowest register requirements. The proposed method has been implemented in an experimental compiler and has been tested for the Perfect Club benchmarks. The results show that the proposed method achieves an optimal II for at least 97.5 percent of the loops and its compilation time is comparable to a conventional top-down approach, whereas the register requirements are lower. In addition, the proposed method is compared with some other existing methods. The results indicate that the proposed method performs better than other heuristic methods and almost as well as linear programming methods, which obtain optimal solutions but are impractical for product compilers because their computing cost grows exponentially with the number of operations in the loop body.

show abstract

Section: Comparison With Other Scheduling Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Modulo scheduling with reduced register pressure

Llosa

Valero

Agyuade

et al. 1998

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…To duplicate the effect of MVE without loop unrolling, Huff proposed an innovative rotating register files as an architectural feature in a hypothetical VLIW processor similar to Cydrome's Cydra 5 [4]. Since Huff technique still requires a large number of architected rotating registers to support MVE without code expansion, Tyson and et al ameliorated Huff technique with register queues and rq-connect instruction [6].…”

Section: Related Workmentioning

confidence: 99%

Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs

Cho

Ayyagari

et al. 2006

Emerging Directions in Embedded and Ubiquitous Computing

View full text Add to dashboard Cite

Abstract. An iterative modulo scheduling is very important for compilers targeting high performance multi-issue digital signal processors. This is because these processors are often severely limited by idle state functional units and thus the reduced idle units can have a positively significant impact on their performance. However, complex instructions, which are used in most recent DSPs such as mac, usually increase data dependence complexity, and such complex dependencies that exist in signal processing applications often restrict modulo scheduling freedom and therefore, become a limiting factor of the iterative modulo scheduler.In this work, we propose a technique that efficiently reselects instructions of an application loop code considering dependence complexity, which directly resolve the dependence constraint. That is specifically featured for accelerating software pipelining performance by minimizing length of intrinsic cyclic dependencies. To take advantage of this feature, few existing compilers support a loop unrolling based dependence relaxing technique, but only use them for some limited cases. This is mainly because the loop unrolling typically occurs an overhead of huge code size increment, and the iterative modulo scheduling with relaxed dependence techniques for general cases is an NP-hard problem that necessitates complex assignments of registers and functional units. Our technique uses a heuristic to efficiently handle this problem in pre-stage of iterative modulo scheduling without loop unrolling.

show abstract

“…We can use either loop unrolling [2], inserting move operations [7], or a hardware rotating register file when available [13] 2 . Therefore, a great amount of work tries to schedule a loop such that it does not use more than R values simultaneously alive [8,22,12,14,11,4,15,6,9]. In this paper we directly work on the loop DDG and modify it in order to satisfy the register constraints for any further subsequent software pipelining pass.…”

Section: Introductionmentioning

confidence: 99%

Early Control of Register Pressure for Software Pipelined Loops

Touati

Eisenbeis

2003

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at first step without assuming a schedule lacks the information of interferences between variable lifetime intervals. Thus, the register allocator may introduce an excessive amount of false dependences that reduce dramatically the ILP (Instruction Level Parallelism). We present a new framework for controlling the register pressure before software pipelining. This is based on inserting some anti-dependences edges (register reuse edges) labeled with reuse distances, directly on the data dependence graph. In this new graph, we are able to guarantee that the number of simultaneously alive variables in any schedule does not exceed a limit. The determination of register and distance reuse is parameterized by the desired critical circuit ratio (MII) as well as by the register pressure constraints -either can be minimized while the other one is fixed. After scheduling, register allocation is done cyclically on conventional register sets or on rotating register files. We give an optimal exact model, and another approximative one that generalizes the Ning-Gao [12] buffer optimization heuristics.

show abstract

Lifetime-sensitive modulo scheduling

Cited by 165 publications

References 21 publications

Modulo scheduling with reduced register pressure

Modulo scheduling with reduced register pressure

Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs

Early Control of Register Pressure for Software Pipelined Loops

Contact Info

Product

Resources

About