Limits on multiple instruction issue

Abstract

This paper investigates the limitations on designing a processor which can sustain an execution rate of greater than one instruction per cycle on highly-optimized, non-scientific applications. We have used trace-driven simulations to determine that these applications contain enough instruction independence to sustain an instruction rate of about two instructions per cycle. In a straightforward implementation, cost considerations argue strongly against decoding more than two instructions in one cycle. Given this constraint, the efficiency in instruction fetching rather than the complexity of the execution hardware limits the concurrency attainable at the instruction level.

Characterizing a new class of threads in scientific applications for high end supercomputers

“…This is similar to other parallelism limit studies [31,20], except that it is targeted towards fine-grain multithreaded PIM systems, in which the threads are primarily identified by the compiler. Threadlets exist within a basic block, which is a sequence of instructions occurring between two branch instructions in the program trace.…”

Customizing VLIW processors from dynamically profiled execution traces

“…Authors have found that block level scheduling has not provided enough parallelism for 8-issue parallelism. Similarly, the results in [34] present that scheduling beyond basic blocks can support performance which is more than two instructions per cycle on average. Nevertheless, this performance is only possible if necessary memory bandwidth is provided.…”

“…Exploring available ILP from a given program has been crucial for application specific VLIW processors in order to reduce compiler effort and prevent redundant hardware. State of the art ILP extraction algorithms are based on either instruction traces [33,6,4,5,[34][35][36][37] or dependency graphs [38,39,15,[40][41][42].…”

The effect of employing advanced branching mechanisms in superscalar processors

“…A recent study reported that in non-numerical programs the average degree of instruction-level parallelism bounded by basic blocks is around 2 [2]. Another independent study generally confirmed this result but also reported that a significant increase in the degree of instruction-level parallelism would result, from 2.3 to 4.1, if control dependence in the programs were removed [3]. This is an interesting result since the increase from 2.3 to 4.1 is almost 80%.…”