Locally switched and limited source-body bias and other leakage reduction techniques for a low-power embedded SRAM

Cserveny, S.; Sumanen, L.; Masgonty, J.-M.; Piguet, Christian

doi:10.1109/tcsii.2005.851781

Cited by 20 publications

(3 citation statements)

References 8 publications

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“…The body-biasing technique known as variable threshold CMOS (VTMOS) uses substrate feedback control circuits to regulate body-source (V BS ) bias [21,22,23,24]. It does not require an external supply source for the substrate biasing, which has zero negative effects on usage or speed.…”

Section: Related Workmentioning

confidence: 99%

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

Banu,

Gupta

2023

Preprint

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The total power in a device is composed of three basic components, having dynamic power due to switching activity, static power while the device in sleep mode and short circuit power while a short amount of current flows from power supply rail (VDD) to ground terminal (GND). The dynamic power component in a CMOS circuit is dominating at lower technology nodes. With scaling, having lesser than 65nm regime the leakage power increases than dynamic power that becomes challenging for the VLSI design engineers. This paper describes a new circuit level leakage power reduction technique called as Input Leakage Controlled Stack Transistor-ILCST for CMOS circuits at circuit level that is been used in 4-bit flash Analog to Digital Converter applicable for deep brain neurostimulator. Analog to Digital Converters (ADC) are crucial for transforming analogue signals from the real world into digital data in the form of 0 and 1. Flash is the most popular ADC owing to its fast speed nature. In this study, a 4-bit flash ADC with a, sample and hold (S/H), comparators and a priority encoder are designed and simulated. To perform sampling process, the sample and hold circuit is utilized. An encoder is a necessary component of a Flash ADC. It converts the comparator output-generated thermometer code (TC) into binary code (BC). The speed, area, and power must all be taken into account while designing the flash analogue to digital converter. Work is implemented using 45nm technology node and carried the simulations in Cadence Virtuoso tool. The static power is reduced significantly using the proposed technique.

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Section: Related Workmentioning

confidence: 99%

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

Banu,

Gupta

2023

Preprint

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“…Regarding the read operation, Verma et al proposed a sense amplifier redundancy technique [9] to mitigate the offset issue during bitline sensing. Finally, leakage reduction is another a topmost requirement in ultra-low power SRAMs since leakage dominates the overall power consumption [10].…”

Section: Introductionmentioning

confidence: 99%

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Kim

Lee

Tuan

2018

Solid-State Electronics

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“…In these applications, SRAMs play a key role in energy consumption due to the high cell density for computational power improvements. One of the most popular ways of obtaining minimum energy consumption is to lower the supply voltage around or below the device threshold voltage[22]. However, lowering supply voltage Research works on optimal SRAM array structures for energy minimization have rarely been conducted.…”

mentioning

confidence: 99%

Low power SRAM-PUF with improved reliability & uniformity utilizing aging impact for security improvement

Garg¹

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Locally switched and limited source-body bias and other leakage reduction techniques for a low-power embedded SRAM

Cited by 20 publications

References 8 publications

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Low power SRAM-PUF with improved reliability & uniformity utilizing aging impact for security improvement

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Locally switched and limited source-body bias and other leakage reduction techniques for a low-power embedded SRAM

Cited by 20 publications

References 8 publications

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Low power SRAM-PUF with improved reliability & uniformity utilizing aging impact for security improvement

Contact Info

Product

Resources

About

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation