2022
DOI: 10.1109/tcad.2021.3121263
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LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing

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Cited by 19 publications
(9 citation statements)
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“…The common ground between GA MOO and TS efficient optimization is that both algorithms begin by randomly initializing some set of data points (Touloupas and Sotiriadis, 2021). However, the GA produces offsprings from parents through the cross-over operation and mutation, while in the TS algorithm, new data points are generated using sample functions from the Gaussian processes.…”
Section: Discussionmentioning
confidence: 99%
“…The common ground between GA MOO and TS efficient optimization is that both algorithms begin by randomly initializing some set of data points (Touloupas and Sotiriadis, 2021). However, the GA produces offsprings from parents through the cross-over operation and mutation, while in the TS algorithm, new data points are generated using sample functions from the Gaussian processes.…”
Section: Discussionmentioning
confidence: 99%
“…Modern EDA tools for HLS, logic synthesis, or physical design synthesis have many parameters, GPR + WEI Amp-1,2 (C-5,C-24), etc., First few apply BO for analog sizing [73] GPR + LCB Amp-1,2 (C-5,C-24), etc., NSGAII solves multi-objective LCB [74] GPR + Acq ensemble Amp-1,2 (C-10,C-12) Batch BO enabled by the ensemble [75] GPR + WEI Op-Amp (C-10), CP (C-36) Neural network as GPR kernel [77] BNN + LCB CP (C-16), Amp (C-13) BNN as surrogate model [76] GPR + WEI Amp (C-5), CP (C-36) Multi-fidelity BO [78] GPC + its Eq. ( 45) Op-Amp(C-4), LNA (C-4) Handles binary testing outputs [82] GPR + WEI CP (C-18, D-5), etc., Modified kernel for D variables [79] GPR + UCB Ampifier-1,2 (C-10,C-12) Asynchronous BO [80] SP-GPR + WEI Amp (C-24), VCO (C-20) Sparse GPR model [81] GPR + EI Op-Amp (variable unknown) Classical BO [88] MT-GPR + WEI Op-Amp (C-10), LNA (C-10) MT-GPR learns multi-performances [83] GPR + TS Amp-1,2,3 (C-23, C-43, C-21)…”
Section: B Other Problems and Discussionmentioning
confidence: 99%
“…( 34) as a new function f (x) with a slight abuse of notation. This treatment is frequently used in analog circuit optimization over multiple process-voltage-temperature (PVT) corners [83]. Namely, in these works, n represents the equivalent variation introduced by the n-th PVT corner and evaluating f (x + n ) will invoke the circuit simulator at the n-th PVT corner.…”
Section: A Schematic-level Circuit Optimizationmentioning
confidence: 99%
“…Efforts to establish means of automation in the analog design cycle include mostly sizing automation approaches [5][6][7][8][9][10]. In this setting, the sizing procedure of a given analog circuit topology is formulated as a black-box optimization problem, where the design space includes all the unknown design variables and the optimization goals and constraints rely on the desired performance metrics.…”
Section: Introductionmentioning
confidence: 99%
“…A low simulation budget alternative is the Bayesian optimization (BO) algorithm [12], which derives good approximations of the optima with relatively fewer evaluations than EAs [12]. BO has been applied to analog circuit sizing, both in the multi-objective [5] and in the single-objective settings [8].…”
Section: Introductionmentioning
confidence: 99%