Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

“…The reduction of metal interconnect thickness increases its resistivity, causing high pad voltage during ESD. With ever-increasing I/O data-rate requirements, capacitance budgets are becoming more stringent [5]. All of these trends exacerbate the shrinkage of the ESD design window [6].…”

Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits

“…Moreover, the largesize diodes with hollow layout styles can achieve comparable level to that of small-size diodes with non-hollow layout style. This result inspires us to consider a way not to continuously shrink the diode size to avoid any capacitance penalty from the junction perimeter [8]- [10]. Although the diode with stripe layout style has the smallest width, its evaluation is not the highest because the diode with stripe layout style cannot give the N+ junction perimeter as much as those of the diodes with other layout styles.…”

“…However, the parasitic loading effects of the ESD protection devices with large device dimension will obviously degrade the circuit performance of signal transmission, especially for radio-frequency (RF) front-end and high-speed input/output (I/O) circuits [6], [7]. In order to reduce the circuit performance degradation, the parasitic capacitance (C ESD ) of the ESD protection devices must be minimized, but the ESD robustness is still kept at the reasonable level [8]. ESD protection designs for RF front-end and high-speed I/O interface circuits must be optimized with consideration of parasitic capacitance and ESD protection capability.…”

Design and optimization of DTSCR for high-speed I/O ESD protection of on-chip ICs

“…With integrated circuit (IC) feature size scaling down, the key features of the electrostatic discharge (ESD) protection design, including the low trigger voltage, small parasitic effect, strong ESD robustness, quick turn-on speed and good voltage clamping ability, is hard to be realized on a high-speed input/output (I/O) of on-chip ICs [1]. The diode string widely serves as ESD protection at I/O terminals of low voltage ICs because * Author to whom any correspondence should be addressed.…”