Low Complexity Generic VLSI Architecture Design Methodology for $N^{th}$  Root and $N^{th}$  Power Computations

Mopuri, Suresh; Acharyya, Amit

doi:10.1109/tcsi.2019.2939720

Cited by 15 publications

(48 citation statements)

References 22 publications

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“…where k stands for test quantity of function X Y . Currently, only [12,14] in the state-of-the-art approaches implement both N √ X and X N computation. For [12,14], the test quantity k is 40,000.…”

Section: Computational Correctnessmentioning

confidence: 99%

“…Currently, only [12,14] in the state-of-the-art approaches implement both N √ X and X N computation. For [12,14], the test quantity k is 40,000. For [14], the number of iterations n is set to be 10.…”

Section: Computational Correctnessmentioning

confidence: 99%

“…For [12,14], the test quantity k is 40,000. For [14], the number of iterations n is set to be 10. For [12], 1024 pieces of result data are stored in either LUT1 or LUT2.…”

Section: Computational Correctnessmentioning

confidence: 99%

“…Therefore, the computation of X Y -like functions can be converted to the computation of logarithmic and exponential functions. The hardware methods of computing X Y -like functions directly or indirectly can be divided into four categories: digit-recurrence [4][5][6], functional iteration [7][8][9], LUT (Look-Up Table )-based [10][11][12], and CORDIC-based [13][14][15]. In fact, CORDIC is one of the digit-recurrence algorithms.…”

Section: Introductionmentioning

confidence: 99%

“…In the latest literatures, Mack et al [27] proposed an expanded hyperbolic CORDIC algorithm to compute powering functions for any FP number. Mopuri and Acharyya [14] did work on N th power computations based on the binary hyperbolic CORDIC, which is a special case of the generalized hyperbolic CORDIC [13]. Luo et al [28] employed the generalized hyperbolic CORDIC to directly compute logarithms and exponentials with an arbitrary fixed base.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs

Liu

Xia

2021

Electronics

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This paper proposes a novel architecture for the computation of XY-like functions based on the QH CORDIC (Quadruple-Step-Ahead Hyperbolic Coordinate Rotation Digital Computer) methodology. The proposed architecture converts direct computing of function XY to logarithm, multiplication, and exponent operations. The QH CORDIC methodology is a parallel variant of the traditional CORDIC algorithm. Traditional CORDIC suffers from long latency and large area, while the QH CORDIC has much lower latency. The computation of functions lnx and ex is accomplished with the QH CORDIC. To solve the problem of the limited range of convergence of the QH CORDIC, this paper employs two specific techniques to enlarge the range of convergence for functions lnx and ex, making it possible to deal with high-precision floating-point inputs. Hardware modeling of function XY using the QH CORDIC is plotted in this paper. Under the TSMC 65 nm standard cell library, this paper designs and synthesizes a reference circuit. The ASIC implementation results show that the proposed architecture has 30 more orders of magnitude of maximum relative error and average relative error than the state-of-the-art. On top of that, the proposed architecture is also superior to the state-of-the-art in terms of latency, word length and energy efficiency (power × latency × period /efficient bits).

show abstract

Section: Computational Correctnessmentioning

confidence: 99%

Section: Computational Correctnessmentioning

confidence: 99%

“…For [12,14], the test quantity k is 40,000. For [14], the number of iterations n is set to be 10. For [12], 1024 pieces of result data are stored in either LUT1 or LUT2.…”

Section: Computational Correctnessmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs

Liu

Xia

2021

Electronics

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show abstract

Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Mopuri

Acharyya

2021

Circuits Syst Signal Process

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Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Changela,

Kumar,

Woźniak

et al. 2023

Sci Rep

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In this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power computations are divided into three phases, and each phase is performed by a different class of the proposed modified radix-4 CORDIC algorithms in the proposed architecture. Although radix-4 CORDIC can converge faster with fewer recurrences, it demands more hardware resources and computational steps due to its intricate angle selection logic and variable scale factor. We have employed the modified radix-4 hyperbolic vectoring (R4HV) CORDIC to compute logarithms, radix-4 linear vectoring (R4LV) to perform division, and the modified scaling-free radix-4 hyperbolic rotation (R4HR) CORDIC to compute exponential. The criteria to select the amount of rotation in R4HV CORDIC is complicated and depends on the coordinates $$X^j$$ X j and $$Y^j$$ Y j of the rotating vector. In the proposed modified R4HV CORDIC, we have derived the simple selection criteria based on the fact that the inputs to R4HV CORDIC are related. The proposed criteria only depend on the coordinate $$Y^j$$ Y j that reduces the hardware complexity of the R4HV CORDIC. The R4HR CORDIC shows the complex scale factor, and compensation of such scale factor necessitates the complex hardware. The complexity of R4HR CORDIC is reduced by pre-computing the scale factor for initial iterations and by employing scaling-free rotations for later iterations. Quantitative hardware analysis suggests better hardware utilization than the recent approaches. The proposed architecture is implemented on a Virtex-6 FPGA, and FPGA implementation demonstrates $$19\%$$ 19 % less hardware utilization with better error performance than the approach with the radix-2 CORDIC algorithm.

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Low Complexity Generic VLSI Architecture Design Methodology for $N^{th}$ Root and $N^{th}$ Power Computations

Cited by 15 publications

References 22 publications

Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs

Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs

Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

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