Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

Vitullo, Francesco; L'Insalata, N.E.; Petri, Esa; Saponara, Sergio; Fanucci, Luca; Casula, Michele; Locatelli, Riccardo; Coppola, Marcello

doi:10.1109/tc.2008.48

Cited by 43 publications

(35 citation statements)

References 19 publications

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“…The future evolution of COTS components in deep scaled technologies (also for IoT) is moving toward multi-core system-on-chip where different macrocells (e.g., processors, memories) are integrated on-chip interconnected through a network on chip [102][103][104][105][106] and/or to application specific processors for sensor conditioning [107][108][109][110]. In such cases, the voltage level requirements will remain more or less the same.…”

Section: Dc/dc Architecture and Circuit-level Designmentioning

confidence: 99%

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

Gutiérrez¹

2017

Electronics

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Abstract:The paper presents a fully-integrated and universal DC/DC converter to minimize cost and size of power supply systems in wireless nodes for Internet-of-Things (IoT) applications. The proposed converter avoids the use of inductors and is made by a cascade of switching capacitor stages, implementing both step-down and step-up converting ratios, which regulate input sources from 1 V to 60 V to a voltage of about 4 V. Multiple linear regulators are placed at the end of the cascade to provide multiple and stable output voltages for loads such as memories, sensors, processors, wireless transceivers. The multi-output power converter has been integrated in a Bipolar-CMOS-DMOS (BCD) 180 nm technology. As case study, the generation of 3 output voltages has been considered (3 V, 2.7 V, and 1.65 V with load current requirements of 0.3 A, 0.3 A, and 0.12 A, respectively). Thanks to the adoption of a high switching frequency, up to 5 MHz, the only needed passive components are flying capacitors, whose size is below 10 nF, and buffer capacitors, whose size is below 100 nF. These capacitors can be integrated on top of the chip die, creating a 3D structure. This way, the size of the power management unit for IoT and CPS nodes is limited at 18 mm 2 . The proposed converter can also be used with changing input power sources, like power harvesting systems and/or very disturbed power supplies.

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Section: Dc/dc Architecture and Circuit-level Designmentioning

confidence: 99%

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

Gutiérrez¹

2017

Electronics

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“…For large chip designs, however, margining results in unacceptable performance degradation when it must account for clock skew and jitter across long on-chip distances, temperature, and process gradients. For this reason, large systems often employ more complex clock designs, such as globally asynchronous, locally synchronous (GALS) clocking schemes, as used in [40,41] to limit the size of the clock domain across which jitter and skew must be tightly controlled. These may be used with wavepipelining [20] or forwarded clock interconnect schemes [21] to resynchronize data at its destination.…”

Section: 5mentioning

confidence: 99%

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

Postman

Chiang

2012

ISRN Electronics

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Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.

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“…Indeed, a NoC aims at bringing on-chip the technologies already developed for computer and telecommunication networks [2,[23][24][25][26][27][28][29][30][31][32][33][34][35][36]. The key building blocks of a NoC are routers [23][24][25][26][27], network interfaces (NI) [28], and links [29][30][31][32][33].…”

Section: Introductionmentioning

confidence: 99%

“…[45][46][47][48][49][50][51][52][53][54][55]. Also, for the Analog-Digital converter [45,55] and for the building blocks of a NoC (e.g., NI, Router, Link in [23][24][25][26][27][28][29][30][31][32][33]) there are many works proposing on-chip integrated solutions. Instead, for the antenna, there are still open issues on optimizing the trade-off between area, gain and bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Gutiérrez¹

2017

JLPEA

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Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

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Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

Cited by 43 publications

References 19 publications

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

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