Low-Density Parity Check Code Concatenated with Generalized Partial Response Equalizer for High-Capacity Magneto-Optic Recording Channels

Song, Hongwei; Liu, Jingfeng; Kumar, B. V. K. Vijaya; Inaba, Akira; Shimazaki, K.; Ota, Norio

doi:10.1143/jjap.41.1749

Cited by 6 publications

(3 citation statements)

References 2 publications

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“…Different devices transmit different carrier frequencies; therefore, PLLs with high accuracy, high stability, fast switching speed, and low power are necessary. 1,5,[13][14][15][16][17] In a conventional analog PLL, the circuit supplies current using the charge pump, converts the current into a voltage to control the voltage-controlled oscillator, and uses passive components. 3,13,18) Therefore, additional time is required to redesign the circuit when it is used with a technology that uses a different process.…”

Section: Introductionmentioning

confidence: 99%

A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

Yang

Wang

Chang

et al. 2020

Jpn. J. Appl. Phys.

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This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self-alignment mechanism to resolve overdamping caused by a large KI. Therefore, the proposed ADPLL not only reduces locking time but also maintains jitter performance. In this paper, we used a 0.18 μm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed ADPLL can reduce locking time by 91%. The output frequency range of the proposed ADPLL is 0.7–1 GHz, which is suitable for sub-GHz Internet of Things band applications. At 1 GHz, the power consumption was 10.93 mW, peak-to-peak jitter was 19.53 ps, locking time was 3.5 μs which is 35 TREF, and core area was 0.291 mm2.

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Section: Introductionmentioning

confidence: 99%

A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

Yang

Wang

Chang

et al. 2020

Jpn. J. Appl. Phys.

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“…[6][7][8][9][10] Recently, iterative equalization and decoding (IED) called turbo equalization have received great attention due to the impressive performance gains for data storage and communication systems. [11][12][13] In HDS systems, various modulation codes have been introduced to mitigate the interference problem in HDS systems. 14) In general, 2D modulation code 15,16) is simply adopted by one-to-one mapping of data words into binary modulation coded rectangles of ON and OFF pixels called symbol.…”

Section: Introductionmentioning

confidence: 99%

Turbo Equalization Scheme between Partial Response Maximum Likelihood Detector and Viterbi Decoder for 2/4 Modulation Code in Holographic Data Storage Systems

Kong

Choi

2012

Jpn. J. Appl. Phys.

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A turbo equalization scheme for holographic data storage (HDS) systems is proposed. The proposed turbo equalization procedure is conducted between a one-dimensional (1D) partial response maximum likelihood (PRML) detector and the joint Viterbi decoder by exchanging a priori and extrinsic information. In the joint Viterbi decoder, the modulation and convolutional decoding is performed simultaneously by mapping a 2/4 modulation symbol onto the trellis of the convolutional code to reduce the complexity of the decoding procedure and improve the decoding capability for the iterative equalization and decoding. In addition, since the channel model is described as the two-dimensional convolution in HDS systems, the 1D PRML detector is performed in the vertical direction and the joint Viterbi decoder is performed in the horizontal direction to maximize the performance gains. The simulation result shows that the proposed turbo equalization scheme has the better bit error rate performances as the number of iterations increases.

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“…They offer more flexibility in the choice of code parameters, and their decoders require simpler processing. These characteristics have made it possible to design appropriate LDPC codes for many communications scenarios; they have been adopted in next generation digital video broadcasting (DVB-S2) via satellite [5], and considered for adoption in wireless local area network (WLAN) air interface (802.11) [6], wireless personal area networks (WPANs) (802.12) [7], mobile broadband wireless access (MBWA) networks (802.20) [8], advanced magnetic and magneto-optic storage/recording systems [9], and long-haul optical communication systems [10]. LDPC codes are linear block codes defined by a sparse parity-check matrix.…”

mentioning

confidence: 99%

A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

Mansour

Shanbhag

2006

IEEE J. Solid-State Circuits

172

105

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Abstract-A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.

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Low-Density Parity Check Code Concatenated with Generalized Partial Response Equalizer for High-Capacity Magneto-Optic Recording Channels

Cited by 6 publications

References 2 publications

A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

Turbo Equalization Scheme between Partial Response Maximum Likelihood Detector and Viterbi Decoder for 2/4 Modulation Code in Holographic Data Storage Systems

A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

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