Low-frequency noise in nanowire and planar III-V MOSFETs

Abstract

Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOS-FETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.

Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications

“…2(b) show the transfer characteristics with temperatures ranging from 300 K to 15 K, respectively, for the vertical InAs/InGaAs GAA MOSFET. A VDS of 50 mV to measure the transfer characteristics was chosen as it is a typical bias for low-frequency noise measurements [11,14,15]. With decreasing T, the absolute value of the threshold voltage (VTH) shifts towards higher values by ≈ 0.5 mV/K (Fig.…”

“…For the LFN measurements, a low-noise preamplifier was used to supply a constant VDS = 50 mV and the current noise power spectral density (PSD) was measured using a lock-in amplifier. A similar setup was used in our previous LFN reports [4,14,15]. The frequency was swept between 1 Hz and 1 KHz and the temperature was varied from 300 K to 15 K. At every temperature point, a gate voltage (VGS) was applied so that the overdrive voltage (VOD = VGS -VTH) was zero [11].…”

“…To address the lack of LFN characterization at cryogenic temperatures, recently, cryogenic 1/f characterization for fully-depleted silicon-on-insulator (FDSOI) MOSFETs was reported [11]. There have been reports on LFN for III-V nanowire MOSFETs at room temperature, but to the best of our knowledge, none yet at cryogenic temperatures [4,[13][14][15][16]. In this work, we present low-frequency noise characterization at temperatures down to 15 K where we demonstrate that the dominant mechanism of 1/f-noise in vertical InAs/InGaAs GAA MOSFETs changes from border and interface trap induced number fluctuations to mobility fluctuations originating from the nanowire core.…”

1/f noise model based on trap-assisted tunneling for ultra-thin oxides MOSFETs

“…The study will focus on carrier number fluctuations, meaning that the noise is caused by the variations of free carriers in the channel due to charge trapping/de-trapping in oxide traps [1]. Mobility fluctuation will not be considered at this stage, given that its contribution is generally less significant [2]. Moreover, also diffusion noises will not be considered, as this paper focuses on 1/f noise only.…”

Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance

“…The estimated N bt is in line with our previous results using different characterization techniques for III-V MOSFET devices, which are typically about an order of magnitude higher compared to state-of-the-art Si devices. 5,6…”