2002
DOI: 10.1109/tcsii.2002.806248
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Low-jitter clock multiplication: a comparison between PLLs and DLLs

Abstract: Abstract-This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output… Show more

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Cited by 57 publications
(49 citation statements)
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“…These errors reduce the amount of HR. In [6] it is shown that static timing errors are typically dominant over dynamic timing errors.…”
Section: A Achievable Harmonic Rejection Ratiomentioning
confidence: 99%
“…These errors reduce the amount of HR. In [6] it is shown that static timing errors are typically dominant over dynamic timing errors.…”
Section: A Achievable Harmonic Rejection Ratiomentioning
confidence: 99%
“…The control loop jitter is usually relatively small [5] and thus ignored hereafter. It has been shown in [5] [6] that for an optimal DLL design, its output jitter is defined by the reference clock and the jitter of a free-running VCDL. The DLL renders no improvement on the reference and VCDL jitter.…”
Section: B Dll Based Mpcg Output Jittermentioning
confidence: 99%
“…Such emerging technologies are expected to soon allow the large-scale integration of array of coupled oscillators paving the way to novel applications. Relevant applications are envisaged in the area of multiphase oscillations for frequency synthesis and clock distribution [4]- [5], noise-mitigation techniques [6] as well as in visionary brain-inspired parallel computing for data analysis and pattern recognition [7]- [12].…”
Section: Introductionmentioning
confidence: 99%