Low-power clock distribution in a multilayer core 3d microprocessor

Abstract

Clock distribution networks are extremely critical from a performance and power standpoint. They account for about 20-30% of the total power dissipated in current generation microprocessors. Many three-dimensional (3D) schemes propose to reduce interconnect length to improve performance and decrease power consumption. In this paper we propose a clock distribution network for a 3D multilayer core microprocessor. The 3D microprocessor floor plan has a single core folded onto multiple layers. A separate layer for the clock distribution network is proposed in the 3D microprocessor. This arrangement of a 3D chip stack reduces (a) power lost in long interconnects at block level and (b) in the clock distribution. Simulation results indicate a 15-20% power saving for this clock distribution scheme as compared to a 2D structure. A methodology for turning off the global clock grid along with the logic for an entire layer in a 3D stack is also proposed. Simulation results indicate an additional 8-10% savings in power with minimal impact on the critical parameters of the clock grid.

Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

“…Arunachalam and Burleson [13] proposed the use of a separate layer for the clock distribution network to reduce power. Their simulations show 15 % to 20 % power reduction over the same 2D chip clock network.…”

“…The procedure is called recursively for each of the subsets S 1 and S 2 with different TSV bounds (lines [11][12]. The roots of the subtrees are connected by the root of the higher-level tree (lines [13][14][15]. The complexity of the algorithm is O(n · logn), where n is the number of nodes.…”

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

“…Temperature dependent clock skew control and power analysis for H-tree based clock network topologies are presented in the works [4][5][6]. Mondal et al [4] proposed a thermally adaptive clocking scheme to reduce the temperature dependent clock skew.…”

“…Mondal et al [4] proposed a thermally adaptive clocking scheme to reduce the temperature dependent clock skew. Arunachalam and Burleson [5] proposed a low power clock design by using a separate layer for the clock network. Pavlidis, Savidis, and Friedman [6] compared clock skew and power consumption for various H-tree based clock network topologies with real measurement data.…”

Clock distribution architectures for 3-D SOI integrated circuits

“…Recent papers consider thermal effects on buffered 3-D clock trees [1] and H-tree topologies [2], [3]. No experimental characterization of 3-D clock distribution networks, however, has been presented.…”