Low Power Consumption Based 4T SRAM Cell for CMOS 130nm Technology

Goyal, A.; Agarwal, Vimal

doi:10.1109/cicn.2016.121

Cited by 3 publications

(1 citation statement)

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“…The DRT was found to be approximately 46µS at 25℃ and 4.7µS for the worst case at 85℃. The retention power which is composed of both the static and refresh power of the proposed GC-eDRAM showed about 80-90% lower consumption than the static power of 6T and 4T ULP SRAMs, which were proposed in [28]. In order to test and evaluate the proposed mixed-𝑉 𝑇 3T GC-eDRAM, a 2Kbit memory array layout was created.…”

Section: Resultsmentioning

confidence: 99%

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Abdo¹,

Alias²,

Hamzah³

et al. 2022

IJIE

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Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-VT 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400MHz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs(others' work in K. Sharma et al.and A. Goyal et al.)the retention power of the proposed GC-eDRAM is around 80-90% lower.

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Section: Resultsmentioning

confidence: 99%