Low power device technology with SiGe channel, HfSiON, and Poly-Si gate

Wang, H.C.-H.; Chen, Shang-Jr; Wang, Mingfang; Tsai, Pang-Yen; Tsai, Cary Chi‐Liang; Wang, Ta‐Wei; Ting, S.M.; Hou, Tuo‐Hung; Lim, Poon Nian; Lin, H.J.; Jin, Y.; Tao, Hun-Jan; Chen, Shih-Chang; Diaz, C.H.; Liang, Mong–Song; Hu, Chenming

doi:10.1109/iedm.2004.1419096

Cited by 14 publications

(9 citation statements)

References 1 publication

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“…These results are plotted in Fig. 2.5 and show close-to-ideal characteristics in comparison with the modeling results of double-gated SOI transistors published in [3] and in the previous experimental data [7,[11][12][13][14][15][16][17][18]. Figure 2.6 shows the inverter transfer function produced by the 4 nm radius and 7 nm effective channel length NMOS and PMOS SNTs.…”

Section: Characteristics Of the Selected Nmos And Pmos Transistorssupporting

confidence: 63%

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Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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In the first chapter of this book, SNTs with dual work function gates were designed and their device characteristics were examined. Later in the same chapter, basic digital CMOS gates were built; their circuit performance, power dissipation, and layout characteristics were analyzed; basic SNT processing steps were shown. A dual work function CMOS technology requires the use of different metals in NMOS and PMOS transistor gates. Finding the appropriate metals that match exactly to the work function values found in this study may often be a difficult enterprise as it may require alloys for gate material or incompatible metals with the SNT processing.One way to reduce the set of problems associated with dual metals is to use a single metal gate. Therefore, this chapter is dedicated to design NMOS and PMOS transistors with a single work function metal gate, and furthermore use these transistors in designing CMOS circuits.As in Chapter 1, this chapter will also introduce the design criteria for SNTs that use a single metal gate, show the design flow to select optimum device dimensions for both NMOS and PMOS transistors, and analyze speed, power dissipation and layout area characteristics of various CMOS logic gates and mega cells that use these devices.The design criteria for the single work function NMOS and PMOS SNTs are very similar to what has been applied to the dual work function SNTs.1. NMOS and PMOS transistors need to have at least 300 mV threshold voltage for 1 V CMOS circuit operation 2. The static OFF current has to be under 1 pA in either NMOS or PMOS transistor

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Section: Characteristics Of the Selected Nmos And Pmos Transistorssupporting

confidence: 63%

“…The amount of DIBL is 114 mV/V for the NMOS and 69 mV/V for the PMOS transistors with 4 nm radius and 7 nm effective channel length. Figure 2.4 shows these values along with previously published data for comparison purposes [3,7,9,11,13,14].…”

Section: Characteristics Of the Selected Nmos And Pmos Transistorsmentioning

confidence: 92%

Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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“…Subthreshold slope is 62 mV/dec for nMOS and 62.5 mV/dec for pMOS transistors at a drain voltage of 1 V. These results are plotted in Fig. 8 and show close-to-ideal characteristics in comparison with Kim's modeling results on double-gated SOI transistors [3] and previously published experimental data [10], [36]- [43]. Fig.…”

Section: G DC Device Characteristics Of the Selected Nmos And Pmos Tsupporting

confidence: 60%

“…These values are shown in Fig. 7 and compared with previously published data [3], [10], [34], [36], [38], [39]. Subthreshold slope is 62 mV/dec for nMOS and 62.5 mV/dec for pMOS transistors at a drain voltage of 1 V. These results are plotted in Fig.…”

Section: G DC Device Characteristics Of the Selected Nmos And Pmos Tmentioning

confidence: 50%

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal

Naresh

Yuan

et al. 2007

IEEE Trans. Nanotechnology

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This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit OFF currents under 1 pA while producing highest ON currents. DC characteristics of the optimum and -channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2-and 3-input NAND, NOR, and XOR gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 m 2 .Index Terms-Low-power very large scale integration (VLSI), metal-gate transistors, nanowire transistors, vertical silicon transistors.

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“…The equivalent oxide thickness is 1.8 nm. Detailed fabrication process and device characteristics were reported in [7] and [8].…”

Section: Introductionmentioning

confidence: 99%

Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs

Tang

Wang

et al. 2007

IEEE Trans. Device Mater. Relib.

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Negative bias-temperature (NBT) stress-induced drain current instability in a pMOSFET with a HfSiON−SiO 2 gate stack is investigated by using a fast transient measurement technique. We find that in certain stress conditions, the NBT-induced current instability evolves from enhancement mode to degradation mode, giving rise to an anomalous turn-around characteristic with stress time and stress gate voltage. Persistent poststress drain current degradation is found in a pMOSFET, as opposed to drain current recovery in its n-type MOSFET counterpart. A bipolar charge trapping model along with trap generation in a HfSiON gate dielectric is proposed to account for the observed phenomena. Poststress single charge emissions from trap states in HfSiON are characterized. Charge pumping and carrier separation measurements are performed to support our model. The impact of NBT stress voltage, temperature, and time on drain current instability mode is evaluated.Index Terms-Bipolar charge trapping, HfSiON, negative bias temperature (NBT) instability, single charge emission.

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Low power device technology with SiGe channel, HfSiON, and Poly-Si gate

Cited by 14 publications

References 1 publication

Single Work Function Silicon Nanowire MOS Transistors

Single Work Function Silicon Nanowire MOS Transistors

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs

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