Low-power reliable SRAM cell for write/read operation

Abstract

Low power SRAM cell is a critical component in modern VLSI systems. The major portion of the power dissipation in the SRAM cell is due to large voltage swing on the bit lines during write operation. In this paper, a low-power reliable (LPR) SRAM cell is proposed for minimizing the power consumption and to enhance the performance. A new write mechanism is proposed to reduce the charging/discharging activity on the respective bit lines. The cell is simulated in terms of power, delay and static noise margin (SNM). The simulated results show that write and read power of the proposed LPR cell are reduced up to 78% and 50% at 0.7 V (in 65 nm technology) respectively compared to the 6T cell. The proposed design achieves 2.4× higher read static noise margin (SNM) than the 6T cell.

Power-up control techniques for reliable SRAM PUF

“…The hold SNM is a metric for measuring the static stability of cross-coupled inverters in the SRAM [19,20]. The hold SNM is defined as the maximum amount of noise that can be tolerated in the SRAM without flipping the state when noise interferes with the bit cell.…”

Novel TCAM-based PUF with improved reliability for hardware-entangled security

“…Conventional 6 T SRAM-PUFs make use of unique characteristics in the transistors of SRAM cells. Due to process variations during manufacturing processes, every transistor in the SRAM cell shows para- metric fluctuations (e.g., threshold voltage variations) [9]. An SRAM cell is composed of two cross coupled inverters connected with two access transistors.…”