Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique

Wang, Jingyu; Liu, Shubin; Shen, Yi; Zhu, Zhangming

doi:10.1109/tcsi.2018.2794465

Cited by 22 publications

(8 citation statements)

References 33 publications

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“…The proposed switching scheme maintains a constant CDAC common mode voltage, which allows a fixed parasitic capacitance on the CDAC top plate. The fixed parasitic capacitance results in a fixed gain error and does not affect the dynamic performance of the ADC [25,26].…”

Section: Capacitive Dacmentioning

confidence: 99%

A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

2018

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This paper reports a 10-bit 150 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bitoverlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm 2 . It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio (SNDR) of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.

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Section: Capacitive Dacmentioning

confidence: 99%

A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

2018

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“…The demand for high-speed and low-power ADCs for battery-operated systems like medical imaging, CMOS image sensors, mobile, and wearable devices are increased substantially in recent years. [1][2][3] Among various ADCs' architectures like pipelined ADCs, deltasigma ADCs, and single-slope ADCs, the successive approximation register (SAR) ADCs are spotted for excellent power efficiency. [4][5][6][7] Furthermore, as the feature size of CMOS devices are scaling down, the conversion rate of SAR ADCs improves.…”

Section: Introductionmentioning

confidence: 99%

“…Analog‐to‐digital converters (ADCs) bridge the physical world to the digital domain. The demand for high‐speed and low‐power ADCs for battery‐operated systems like medical imaging, CMOS image sensors, mobile, and wearable devices are increased substantially in recent years 1–3 . Among various ADCs' architectures like pipelined ADCs, delta‐sigma ADCs, and single‐slope ADCs, the successive approximation register (SAR) ADCs are spotted for excellent power efficiency 4–7 .…”

Section: Introductionmentioning

confidence: 99%

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

Pahlavanzadeh

Karami

2023

Circuit Theory & Apps

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Summary This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM.

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“…Successive approximation register (SAR) analogue to digital converter (ADC) always attracts the attention of the researchers. At present, low-power SAR ADCs are used in programmable logic control (PLC)and image/multi-sensor applications (Wang et al, 2018;. Scientists are working hard to make it efficient in all categories, especially in the area of energy, power and time.…”

Section: Introductionmentioning

confidence: 99%

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Faheem

Zhong

Wang

et al. 2020

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Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique

Cited by 22 publications

References 33 publications

A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

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