Low voltage sensing techniques and secondary design issues for sub-90nm caches

Sinha, M.; Hsu, S. H.; Alvandpour, Atila; Burleson, Wayne; Krishnamurthy, Rahul; Borkar, S.

doi:10.1109/esscirc.2003.1257160

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…Genuine current-mode sense-amplifiers have been employed in SRAM applications, where speed is critical during read operation and voltage swings are problematic due to sizing limitation of the bit line drivers [29]- [31]. Similar solutions are applied to global interconnect and are reported to dissipate less power and achieve higher throughput than an interconnect buffered with an optimal number of repeaters [32]- [36].…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Current Mode Serial Communication

Dobkin

Moyal

Kolodny

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

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Section: Introductionmentioning

confidence: 99%

Asynchronous Current Mode Serial Communication

Dobkin

Moyal

Kolodny

et al. 2010

IEEE Trans. VLSI Syst.

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“…The voltage-mode circuits included in the study were Cross-coupled Inverter Latch (C2IL) [2] and Alpha Latch [3] and the current-mode included Clamped Bitline Sense Amplifier (CBLSA) [4] and Modified Differential Current Sense Amplifier (MDCSA) [5]. A Charge Transfer Sense Amplifier (CTSA) [5] is also compared. All the circuits were studied for various column heights and were tested for the worst case bitline leakage.…”

Section: Comparison Of Sense Amplifiersmentioning

confidence: 99%

Sensing Design Issues in Deep Submicron CMOS SRAMs

Natarajan

Shankar

Maheshwari

et al.

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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In this paper, solutions to memory design issues in nanometer CMOS are presented. First a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved Bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of upto 68% can be obtained using this technique.

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