Lowest variability SOI FinFETs having multiple V&lt;inf&gt;t&lt;/inf&gt; by back-biasing

Matsukawa, Takashi; Fukuda, Kenji; Liu, Y.X.; Endo, Kazuhiko; Tsukada, Junichi; Yamauchi, H.; Ishikawa, Yoshihiro; O’uchi, S.; Mizubayashi, Wataru; Migita, Shinji; Morita, Yukinori; Ota, Hiroyuki; Masahara, Meishoku

doi:10.1109/vlsit.2014.6894393

Cited by 11 publications

(8 citation statements)

References 3 publications

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“…μm (Fig. 8a), which is close to the state-of-the-art for undoped thin film CMOS technologies [22] [26] [27]. The current gain factor matching parameter Δ is almost 50% larger than typical stateof-the-art values [22].…”

Section: Matching Analysissupporting

confidence: 71%

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

Catapano

Ghibaudo

Cassé

et al. 2021

IEEE J. Electron Devices Soc.

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This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Yfunction method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

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Section: Matching Analysissupporting

confidence: 71%

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

Catapano

Ghibaudo

Cassé

et al. 2021

IEEE J. Electron Devices Soc.

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“…Hence, SOI based FinFETs are the center of attraction nowadays. Detailed studies of SOI based FinFETs are presented in [12][13][14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

“…Constructing tri-gate FinFETs different approaches has been followed in recent years like SOI based FinFETs, bulk FinFET [6][7][8][9][10][11][12][13][14][15][16][17][18]. The inverted-T structure FinFET [19] is also designed which provides better drain current compared to the SOI based FinFET.…”

Section: Introductionmentioning

confidence: 99%

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Tripathy

Acharya

Rout³

et al. 2022

FACTA U EE

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This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is a reduction in oxide (SiO2) layer thickness. The parameters like energy and consumed power of FinFET get better when the oxide (SiO2) layer thickness increases.

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“…Hence, SOI based FinFETs are the center of attraction now-a-days. The detail study of the SOI based FinFETs are presented in [19][20][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

Tripathy

Pk³

2021

Preprint

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In this paper, the influence of oxide (SiO2) layer thickness on the different figure of merits of a FinFET is analysed by varying the oxide layer thickness which is present between the gate and the Fin. Here, the overall thickness of the FinFET is taken to be 30nm, and the oxide (SiO2) layer thickness is changed from 0.8 nm to 3nm, and the analog, radio frequency parameters are determined for different structures. The performance parameters like drain current (ID), transconductance generation factor (TGF), transconductance (gm), output conductance (gds), parasitic capacitances like Cgs, Cgd, Cgg, cut-off frequency (fT), gain bandwidth product (GBW) and maximum frequency of oscillation (fmax) are calculated to learn the influence of variation in the FinFET oxide (SiO2) layer thickness. It is detected from the result and analysis that the drain current, output conductance, transconductance generation factor, transconductance and gain bandwidth product improve with decrement in oxide layer thickness. But as a tradeoff, the internal capacitances like Cgs, Cgd, Cgg, maximum frequency of oscillation and cut-off frequency degrade when there is a reduction in oxide (SiO2) layer thickness.

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Lowest variability SOI FinFETs having multiple V<inf>t</inf> by back-biasing

Cited by 11 publications

References 3 publications

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

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