&lt;title&gt;Fast proximity correction with zone sampling&lt;/title&gt;

“…Top among them are immersion technology where a droplet of fluid alters the effective index of refraction of the applied lens making the effective wavelength of the source light smaller; lenses with higher numerical apertures; double exposure techniques, off-axis illumination, and phase-shift masks, etc. EDA tools through implementing RET with its main two components of OPC [4] and PSM [5] assignment is doing its share of extending the usefulness of the 193nm lithography. OPC involves adding layout artifacts (model based) to restore dimensional accuracy.…”

Section: Lithographymentioning

confidence: 99%

EDA Challenges in Nano-scale Technology

Kawa

Chiang

Camposano

2006

IEEE Custom Integrated Circuits Conference 2006

View full text Add to dashboard Cite

Since the onset of the 90 nm node the challenges associated with further transistor scaling while maintaining a consistently functional, reliable, and yielding design have increased substantially. While those challenges carry across the spectrum of the manufacturing, the EDA, and the design communities, we believe it is the responsibility and the goal of the EDA industry to deal with those issues as thoroughly and as seamlessly as possible to make those challenges transparent to the designer. In this paper we expose and analyze a plurality of those challenges and briefly go over the solutions EDA tools are offering for dealing with them. We also look forward and cover some of the future challenges associated with the integration of the emerging bottoms-up nano-materials flow with the traditional CMOS top-down process flow which has also entered the nano-era.

show abstract

“…In our approach, we aim at dividing the input parameter distribution space into different strata/zones [16]. The strata are regions over which the parameter variation is not more than 0.25σ.…”

Section: Process Parameter Variation Using Stratified Samplingmentioning

confidence: 99%

On linewidth-based yield analysis for nanometer lithography

Sreedhar

Kundu

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

Lithographic variability and its impact on printability is a major concern in today's semiconductor manufacturing process. To address sub-wavelength printability, a number of resolution enhancement techniques (RET) have been used. While RET techniques allow printing of sub-wavelength features, the feature width itself becomes highly sensitive to process parameters, which in turn detracts from yield due to small perturbations in manufacturing parameters. Yield loss is a function of random variables such as depth-of-focus and exposure dose. In this paper, we present a first order canonical dose/focus model that takes into account both the correlated and independent randomness of the effects of lithographic variation. A novel tile-based yield estimation technique for a given layout, based on a statistical model for process variability is presented. Another novel contribution of this paper is the computation of global and local line-yield probabilities. The key issues addressed in this paper are (i) layout error modeling, (ii) avoidance of mask simulation for chip layouts, (iii) avoidance of full Monte-Carlo simulation for variational lithography modeling, (iv) building a methodology for yield estimation based on existing commercial tools. Numerical results based on our approach are shown for 45nm ISCAS85 layouts.Keywords-Photolithography, depth-of-focus, exposure dose, focus-exposure matrix (FEM), chemical mechanical polishing, stratified sampling, linewidth-based yield.

show abstract

<title>Fast proximity correction with zone sampling</title>

Cited by 53 publications

References 0 publications

Optical lithography—a historical perspective

Optical lithography—a historical perspective

EDA Challenges in Nano-scale Technology

On linewidth-based yield analysis for nanometer lithography

Contact Info

Product

Resources

About