Mapping of mechanical, thermomechanical and wire-bond strain fields in packaged Si integrated circuits using synchrotron white beam X-ray topography

Abstract

Abstract-Thermal processing steps used during the production of packaged integrated circuits can lead to severe thermomechanical stresses. In addition, the process of bonding wires to contact pads can also lead to strain field generation. A feasibility study using the application of white beam synchrotron x-ray topography to packaged erasable programmable read-only memory (EPROM) Si integrated circuits (ICs) has been undertaken in order to produce maps of the strain fields induced by such processing steps. This technique provides depth-resolved mapping with spatial resolutions currently in the region of 5-10 m throughout the entire mapping volume. Furthermore, the use of different experimental geometries allows the user to nondestructively probe the strain fields present at the wafer surface right through to the back side.

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

“…Topographs were recorded on a high resolution Slavich VRP-M holographic film (grain size <0.04 μm) set 80 mm from the sample in back-reflection geometry [3]. LauePT software [25] was used to index the Laue spots in the individual topographs.…”

“…The fabrication process of a complete packaged IC is a tricky one, as it involves the use of different materials of distinct coefficients of thermal expansion (CTEs), e.g. die bond pad, die attach adhesive/epoxy glue, moulding compounds and Cu-filled through-silicon-vias (TSVs) [2][3][4][5][6]. Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11].…”

“…Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11]. Other factors such as the bonding of wires to the die itself [3], thinning of the wafer/die below 100 µm and embedding/lamination processes can also lead to stress and induced warpage/material deformation [12][13]. The process-induced stresses can even be large enough to induce cracking or interfacial delamination in the package, which by potentially degrading the performance and reliability of the packaged chip, could ultimately lead to device failure.…”

Structural investigation of MOVPE-grown GaAs on Ge by x-ray techniques

“…L is measured manually from each topograph and volume, V, can be easily calculated using the beam spot size and X-ray penetration depth, t p . For back reflection SXRT, the t p into the sample for each reflection can be calculated based on conventional kinematical theory [15,22] ( 2) where is the incident grazing angle, is the exit grazing angle and is the wavelength-dependent absorption constant for the material. From equations (1) and (2), the dislocation density is then calculated accordingly.…”

Femtosecond versus nanosecond laser micro-machining of InP: a nondestructive three-dimensional analysis of strain

“…Using transmission section topography (TS) geometry, a set of cross-section images of the strain distribution on different crystal planes can be obtained in a few minutes. SXRT has already been successfully used to characterize the defects in single crystal Si, thermal processing induced strain fields in packaged Si integrated circuits and solder bump process induced stress distributions in Si substrates [9][10][11]. One drawback to be noted at this stage is that it is normally very difficult to determine the sign of the strain which produced the contrast on the recording film and only the magnitude of the strain can be calculated based on SXRT results.…”