Measurement and simulation of junction to board thermal resistance and its application in thermal modeling

Joiner, B.; Adams, V.

doi:10.1109/stherm.1999.762450

Cited by 19 publications

(5 citation statements)

References 9 publications

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“…2) Lump each of these segments to a single block with effective properties 3) After simplification, consider using thin plate objects 1 as much as possible in order to minimize the unaligned edges and sources of thin computational cell elements. The image of the details of a typical full and peripheral array BGA are shown in Figs.…”

Section: A Compact Conduction Model Generation Proceduresmentioning

confidence: 99%

“…1) Identification of Distinct Objects or Arrays of Objects Forming a Conduction Pathway: Die, Die flag, die attach, 1 Contact resistance plates and conducting thin plates are CFD modeling objects that help eliminate thin computational cells. Contact resistance plates [16] are 1-D heat flow model used to impose a temperature decrease in the direction of heat flow based on the heat flow rate and the specified resistance.…”

Section: A Compact Conduction Model Generation Proceduresmentioning

confidence: 99%

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Compact conduction model of ball grid array packages

Refai-Ahmed¹,

Karimanal

2003

IEEE Trans. Comp. Packag. Technol.

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This work focuses the application of compact conduction model (CCM) creation approach to ball grid array (BGA) packages under steady state conditions. The procedure of creating CCM from detailed BGA model is demonstrated. The authors have imposed realistic boundary condition scenarios that are likely to test the boundary condition independence necessary for the compact modeling approach. Results showed acceptable agreement in die temperature and heat flow predictions from simulations using detailed BGA models and their CCM equivalents.

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Section: A Compact Conduction Model Generation Proceduresmentioning

confidence: 99%

Section: A Compact Conduction Model Generation Proceduresmentioning

confidence: 99%

Compact conduction model of ball grid array packages

Refai-Ahmed¹,

Karimanal

2003

IEEE Trans. Comp. Packag. Technol.

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“…What is described here is the benchmarking of The probable reason for this trend is the effectively larger surface area for radiative and convective heat transfer from the top surface of the compact thermal model compared to the detailed model, as described by Joiner and Adams [5]. As expected, the more complex Delphi thermal resistance model provided better agreement with the detailed model compared to the 2-resistor thermal model.…”

Section: Discussion and Resultsmentioning

confidence: 57%

A study of compact thermal model topologies in CFD for a flip chip plastic ball grid array package

Shidore

Adams

Lee

ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH3

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Phone: (5 12) 420-9273Austin, TX Tempe, A 2 ABSTRACT A previously validated detailed model of a 119-pin Flip-Chip Plastic Ball Grid Array (FC-PBGA) package was created and validated against experimental data for natural convection and forced coirvection environments. Next, two compact models were derived, a two-resistor model (created using the JEDECstandard based computational approach), and a multi-resistor model (created using the DELPHI optimization approach that was boundary condition independent within engineering accuracy). The compact models were placed in natural convection and forced convection (velocities of 1 and 2 m/s) environments with and without a heatsink. Based on the agreement obtained between the detailed model and compact model simulations, the accuracy and validity of the two compact models was assessed. Of the two compact thermal models considered, the Delphi multi-resistor model provided the same predictive estimates (within 5 % ) as simulations involving a detailed thermal model of the package in natural and forced convection environments both with and without attached heatsinks. Some thermal modeling issues were addressed with respect to implementation of compact thermal models with attached heatsinks. IN TR 0 D U CTIO NCreating validated thermal models of electronic packages has always been a challenge in the electronics industry. Existing metrics such as junction-to-case thermal resistance and junction-to-am bient thermal resistance are sometimes useful as figures of merit, but have proven to fail spectacularly in many real environments (Dutta [l]). This is because these measures typically are reported for ill-defined boundary conditions, and are also by definition subject to large variations depending on the environment.In order to improve the ability of design engineers to model electronic parts successfully, project DELPHI (Development of Physical models for an Integrated design environment) was launched in 1993 by several European end-users with the specific aim of creating a methodology for the generation of thermal models that would be independent of the environmental boundary conditions (Rosten and Lasance [2]). This project has produced an established methodology for creation of two types of thermal modelsa "detailed" model (representing the package in sufficient geometric detail so as to capture all relevant thermal paths accurately; KEY WORDS: electronic package, component-leve] thermal and a "compact" model (a much reduced model consisting of a thermal resistance network that would still capture the thermal behavior of the parts accurately, and predict die-junction temperatures to a high behavioral model; air cooling; plastic ball grid array; compact model, thermal resistance NOMENCLATURE Therm a1 conductivity, (W/[m KI) k P Power, (W)

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“…The thermal network data for various types of IC packaging are available from published literature [1][2][3][4][5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Integration of thermal compact models into finite element simulation of printed wiring assemblies

Haller

Neumaier

Khan³

et al.

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545)

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In this paper a strategy for the integration of boundary condition independent (BCI) thermal compact models in board-level static thermal finite element (FE) analyses of printed wiring assemblies (PWA) is presented. This concept is an integral part of a software development project for automatic investigation of solder joint fatigue of surface mount devices (SMT). The overall automation process comprises data capture for PWA, layout data repair and session control for finite element analysis (FEA).Solder joint fatigue results from thermo-mechanical stresses. For this reason both board-and component-level thermal simulations are needed. Among other component descriptions BCI thermal compact models can be automatically incorporated into FE models replacing detail FE modeling of IC packages. This approach has been investigated in various test examples. A further application of this approach to transient simulations seems to be possible.

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Measurement and simulation of junction to board thermal resistance and its application in thermal modeling

Cited by 19 publications

References 9 publications

Compact conduction model of ball grid array packages

Compact conduction model of ball grid array packages

A study of compact thermal model topologies in CFD for a flip chip plastic ball grid array package

Integration of thermal compact models into finite element simulation of printed wiring assemblies

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