Measurement and simulation of stacked die thermal resistances

Joiner, B.; De, Jiang; Neelakantan, S.

doi:10.1109/stherm.2006.1625230

Cited by 13 publications

(3 citation statements)

References 9 publications

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“…In this work, heat transfer is considered to be one-dimensional, and also, the effect of convective heat transfer is neglected, which may not be realistic. Furthermore, the total thermal resistance between junctions and ambient has been calculated, while the effect of thermal resistance of every attachment on the thermal performance has not been considered [45]. In another study, microbump thermal resistance in a four-layer chip stack has been measured experimentally with and without underfill materials and the effect of microbump pitches on the thermal resistance has been investigated [40].…”

Section: Introductionmentioning

confidence: 99%

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

Choobineh

Jones

Jain

2017

Journal of Electronic Packaging

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Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

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Section: Introductionmentioning

confidence: 99%

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

Choobineh

Jones

Jain

2017

Journal of Electronic Packaging

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“…But it is a bit too complex to handle multiple or distributed heat sources, besides its inability to obtain the temperature distribution of whole structure. In , the entire heat dissipation path is treated as one or several thermal resistors. However, this method has similar shortcomings as CTM, especially for complex structures and applications, such as SoPs.…”

Section: Introductionmentioning

confidence: 99%

Steady-state electro-thermal analysis and optimization of multilayer boards and substrate-integrated waveguide filters

Zhang

Qiu

et al. 2014

Int J RF and Microwave Comp Aid Eng

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An efficient method is proposed to perform the steady‐state thermal analysis of multilayer boards by using the multilayer finite‐difference method to obtain and solve the thermal conductance network. The electro‐thermal analysis of substrate‐integrated waveguide (SIW) filter is further carried out, with its distributed heat source, that is, electromagnetic losses. Then, our method is applied to optimize the electro‐thermal performance of a composite configuration, including a SIW filter with a selfheating chip attached on it. A location with the minimum hotspot temperature is found. Good agreement is achieved between the results simulated with our method and the commercial finite element method (FEM) simulators. When the worst‐case error is set to 5.3%, the run time of our method is significantly reduced by 95% in comparison with the FEM simulators. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:594–604, 2014.

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“…A recent tendency is to measure the temperature change on all chips in the package and to report the results of all these measurements. In what format and with what content this reporting should be done, is still open to discussion [9], but measuring and reporting a full thermal resistance matrix [7], [8] or thermal impedance matrix [6], [10] seems to gain wider acceptance among different thermal research teams. The attempts to create thermal models out of measurement results include resistor networks with a few elements only [5], [7] or providing the network representation of the complete thermal resistance matrix [8] or providing all the elements of the thermal impedance matrix by means of time-domain or frequency-domain functions [6], [10] or even by means of a dynamic compact model derived from structure functions [10].…”

Section: Introductionmentioning

confidence: 99%

Thermal Measurement and Modeling of Multi-Die Packages

Poppe

Zhang

Wilson

et al. 2009

IEEE Trans. Comp. Packag. Technol.

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Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study we present results for a more complex structure: an opto-coupler device with 4 chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and MCM structures. It describes actual measurement results along with our structure function based methodology which helps validating the detailed model of the package being studied. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions.

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Measurement and simulation of stacked die thermal resistances

Cited by 13 publications

References 9 publications

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

Steady-state electro-thermal analysis and optimization of multilayer boards and substrate-integrated waveguide filters

Thermal Measurement and Modeling of Multi-Die Packages

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