Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

Harada, Reiko; Mitsuyama, Yukio; Hashimoto, Masanori; Onoye, Takao

doi:10.1587/transfun.e93.a.2417

Cited by 10 publications

(4 citation statements)

References 16 publications

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“…been developed [179], [182], [185], [192], [204]- [206], and many of them rely on a Time-to-Digital Converter (TDC), as conceptually illustrated in Fig. 18(a).…”

Section: Invertermentioning

confidence: 99%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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“…been developed [179], [182], [185], [192], [204]- [206], and many of them rely on a Time-to-Digital Converter (TDC), as conceptually illustrated in Fig. 18(a).…”

Section: Invertermentioning

confidence: 99%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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“…This 230-stage VDL was designed to achieve 4.8 ps time resolution. The number of stages in VDL is determined so that the measurable range of SET pulse-width can cover the pulse-widths reported in literature [7], [8]. The upper bound of measurable pulse-width is about 10 ns.…”

Section: Irradiation Experiments and Calibrationmentioning

confidence: 99%

“…Using this structure, while we can suppress the pulse-width modulation by using short inverter chains, we can increase the area ratio of the target circuit to the measurement circuit. Among circuits previously proposed for pulse-width measurement, we selected a two-stage measurement circuit that consists of a pulse-to-time converter and a time-to-digital converter [7]. In this work, Vernier delay line (VDL) is used as the time-to-digital converter.…”

Section: Introductionmentioning

confidence: 99%

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

Harada

Mitsuyama

Hashimoto

et al. 2014

IEICE Trans. Fundamentals

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This paper presents a measurement circuit structure for capturing SET pulse-width suppressing pulse-width modulation and within-die process variation effects. For mitigating pulse-width modulation while maintaining area efficiency, the proposed circuit uses massively parallelized short inverter chains as a target circuit. Moreover, for each inverter chain on each die, pulse-width calibration is performed. In measurements, narrow SET pulses ranging 5 ps to 215 ps were obtained. We confirm that an overestimation of pulse-width may happen when ignoring die-to-die and within-die variation of the measurement circuit. Our evaluation results thus point out that calibration for within-die variation in addition to die-to-die variation of the measurement circuit is indispensable. key words: soft error, single event transient (SET), pulse-width, pulsewidth modulation, measurement circuit, within-die process variation Ryo Harada (S'09) received the B.E. and M.E. degrees in Information Systems Engineering from Osaka University, Osaka, Japan, in 2009. He is currently pursuing the Ph.D. degree in the Department of Information Systems Engineering at Osaka University. His research interests include soft error estiomation. Yukio Mitsuyama received B.E., M.E., and Ph.D. degrees in Information Systems Engineering from Osaka University, Japan, in 1998, 2000, and 2010, respectively. He is currently an Associate Professor in School of Engineering, Kochi University of Technology. His research interests include reconfigurable architecture and its VLSI design. He is a member of IEEE and IPSJ. sity. His research interest includes computeraided design for digital integrated circuits, and high speed and low power circuit design. Dr. Hashimoto served on the technical program committees for international conferences including DAC, ICCAD, ITC, Symposium on VLSI Circuits, ASP-DAC, DATE, and ISPD. He is a member of IEEE, ACM and IPSJ. Takao Onoye received the B.E. and M.E. degrees in Electronic Engineering, and Dr.Eng. degree in Information Systems Engineering all from Osaka University, Japan, in 1991Japan, in , 1993Japan, in , and 1997. He is currently a professor in the Department of Information Systems Engineering, Osaka University. His research interests include media-centric low-power architecture and its SoC implementation. He is a member of IEEE, IPSJ, and ITE-J.

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“…Using this structure, while we can suppress the pulse-width modulation by using short inverter chains, we can increase the area ratio of the target circuit to the measurement circuit. Among circuits previously proposed for pulse-width measurement, we select a two-stage measurement circuit that consists of a pulse-to-time converter and a time-todigital converter [5]. In this work, Vernier delay line (VDL) is used as the time-to-digital converter.…”

Section: Introductionmentioning

confidence: 99%

SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

Harada

Mitsuyama

Hashimoto

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Abstract-This paper presents a measurement circuit structure for capturing SET pulse-width suppressing pulse-width modulation and within-die process variation effects. For mitigating pulse-width modulation while maintaining area efficiency, the proposed circuit uses massively parallelized short inverter chains as a target circuit. Moreover, for each inverter chain on each die, pulse-width calibration is performed. In measurements, narrow SET pulses ranging 5 ps to 215 ps were obtained. We confirm that an overestimation of pulse-width may happen when ignoring die-to-die and within-die variation of the measurement circuit. Our evaluation results thus point out that calibration for within-die variation in addition to die-to-die variation of the measurement circuit is indispensable.

show abstract

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

Cited by 10 publications

References 16 publications

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

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