Memory optimization in single chip network switch fabrics

Whelihan, David; Schmit, Herman

doi:10.1145/513918.514052

Cited by 8 publications

(7 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section we show a subset of the experiments, pertaining to a 2-D torus, developed to show the implications and trade-offs of coarse grain design decisions. Other results can be found in [8]. The model used there was derived from the one described here.…”

Section: Simulation Resultsmentioning

confidence: 99%

System-level modeling of a network switch SoC

Paul

Andrews

Cassidy

et al. 2002

Proceedings of the 15th International Symposium on System Synthesis - ISSS '02

View full text Add to dashboard Cite

We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a design team consisting of an experienced network switch designer and an experienced VLSI hardware designer. After facilitating the design process, the CAD team observed how designers approach highlevel designs, beyond RTL. We motivate the need for CAD support that allows designers to effectively manipulate what we refer to as Memory Visualization Level (MVL) design.

show abstract

Section: Simulation Resultsmentioning

confidence: 99%

System-level modeling of a network switch SoC

Paul

Andrews

Cassidy

et al. 2002

Proceedings of the 15th International Symposium on System Synthesis - ISSS '02

View full text Add to dashboard Cite

show abstract

“…Pinto et al [18] presents a heuristic for the constraint-driven communication synthesis of on-chip communication networks, while [20] describes a design methodology for finding minimal topologies that support low contention or contention-free communication for known communication patterns. In [19], memory optimization in single chip network fabrics is explored.…”

Section: Previous Workmentioning

confidence: 99%

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

Bertozzi

Jalabert

Murali

et al. 2005

IEEE Trans. Parallel Distrib. Syst.

480

219

View full text Add to dashboard Cite

The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of network-on-chip (NoC) architectures that have been proposed recently for system-on-chip (SoC) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler). The entire flow leverages the flexibility of a fully reusable and scalable network components library called xpipes, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented In the work, showing the powerful design space exploration capabilities of the proposed methodology and tools

show abstract

“…Throughput Loss We considered aggregate accesses from 2 write and 2 read ports 3 . By serializing the accesses from the 4 ports in a round-robin manner we measured the throughput loss presented in Table 1.…”

Section: No Optimization Optimization Throughput Lossmentioning

confidence: 99%

“…Write access delay = 40 ns, Read access delay = 60 ns. When write accesses occur after read accesses, the write access must be delayed 1 access cycle 3. A write and a read port from/to the network, a write and a read port from/to an internal processing unit.Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE…”

mentioning

confidence: 99%

Queue Management in Network Processors

Papaefstathiou

Orphanoudakis

Kornaros

et al.

Design, Automation and Test in Europe

View full text Add to dashboard Cite

One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we analyze the performance bottlenecks of various data memory managers integrated in typical Network Processing Units (NPUs). We expose the performance limitations of software implementations utilizing the RISC processing cores typically found in most NPU architectures and we identify the requirements for hardware assisted memory management in order to achieve wire-speed operation at gigabit per second rates. Furthermore, we describe the architecture and performance of a hardware memory manager that fulfills those requirements. This memory manager, although it is implemented in a reconfigurable technology, it can provide up to 6.2Gbps of aggregate throughput, while handling 32K independent queues.

show abstract

Memory optimization in single chip network switch fabrics

Cited by 8 publications

References 16 publications

System-level modeling of a network switch SoC

System-level modeling of a network switch SoC

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

Queue Management in Network Processors

Contact Info

Product

Resources

About