Memristive Logic‐in‐Memory Integrated Circuits for Energy‐Efficient Flexible Electronics

Jang, Byung Chul; Nam, Yunyong; Koo, Beom Jun; Choi, Junhwan; Im, Sung Gap; Park, Sang‐Hee Ko; Choi, Sung‐Yool

doi:10.1002/adfm.201704725

Cited by 65 publications

(55 citation statements)

References 53 publications

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“…For neuromorphic applications, however, it is desirable to program different resistances during the set as well as during the reset operation. An suitable approach is the reduction of the voltage divider effect to emphasize the intrinsic gradual reset transition, e. g. by introducing a selector element with an asymmetric I-V characteristics 47,48 . For the set mode, this selector should limit the current and define the programmed resistance.…”

Section: Discussionmentioning

confidence: 99%

Picosecond multilevel resistive switching in tantalum oxide thin films

Böttger

Witzleben

Havel

et al. 2020

Sci Rep

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The increasing demand for high-density data storage leads to an increasing interest in novel memory concepts with high scalability and the opportunity of storing multiple bits in one cell. A promising candidate is the redox-based resistive switch repositing the information in form of different resistance states. For reliable programming, the underlying physical parameters need to be understood. We reveal that the programmable resistance states are linked to internal series resistances and the fundamental nonlinear switching kinetics. The switching kinetics of $$\hbox {Ta}_2 \hbox {O}_5$$ Ta 2 O 5 -based cells was investigated in a wide range over 15 orders of magnitude from 10$$^5$$ 5 s to 250 ps. The capacitive charging time of our device limits the direct observation of the set time below 770 ps, however, we found indication for an intrinsic switching speed of 10 ps at a stimulus of 3 V. On all time scales, multi-bit data storage capabilities were demonstrated. The elucidated link between fundamental material properties and multi-bit data storage paves the way for designing resistive switches for memory and neuromorphic applications.

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Section: Discussionmentioning

confidence: 99%

Picosecond multilevel resistive switching in tantalum oxide thin films

Böttger

Witzleben

Havel

et al. 2020

Sci Rep

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“…11. The steps are 1) Majority at col. (1,9,26,33,42,49,58,65). In the above mapping, it must be noted that each bitwise majority operation is a READ operation and it must be followed by WRITE to be used as an input to the next logic level.…”

Section: B Mapping Of the Eight-bit Pp Adder To 1t-1r Arraymentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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“…8 to a 1T-1R array, using the proposed logic family, and elaborate the sequence of operations. Since the proposed gates are not stateful 4 , the output of the majority 4 In memristive logic, a logic family is said to be stateful if both the input and output of a computation are represented as resistance of the RRAM/memristor [7] A(a n-1 a n-2 . .…”

Section: B Mapping Of the Eight-bit Lf Adder To 1t-1r Arraymentioning

confidence: 99%

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

Reuben

Pechmann

2020

2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Efforts to combat the 'von Neumann bottleneck' have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it's expressive power. In this work, we propose a method to compute majority while reading from a transistoraccessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs' resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively. Index Terms-Resistive RAM (RRAM), majority logic, majority gate, memristor, 1 Transistor-1 Resistor(1T-1R), von Neumann bottleneck, in-memory computing, compute-in-memory, processing-in-memory, parallel-prefix adder This is author's version of the accepted paper. For the published paper, see the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) proceedings in https://ieeexplore.ieee.org/ See Conference presentation (20 min video) at https://asap2020.cs.manchester.ac.uk/paper.php?id=72

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Memristive Logic‐in‐Memory Integrated Circuits for Energy‐Efficient Flexible Electronics

Cited by 65 publications

References 53 publications

Picosecond multilevel resistive switching in tantalum oxide thin films

Picosecond multilevel resistive switching in tantalum oxide thin films

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

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