Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

Anomalous VFB Shift in High-k Gate Stacks - Is its Origin at the Top or Bottom Interface ? -

“…Fully silicided metal (FUSI) gates have attracted much attention in terms of their process compatibility with conventional poly-Si technology in scaled CMOSFETs (16). It was reported that another advantage of the FUSI process was V TH controllability using the impurity segregation near the surface of the SiO 2 dielectric in FUSI/SiO 2 MOSFETs.…”

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

“…Undesirable coupling effects between drain and channel can be suppressed by using Silicon on Insulator (SOI) or Silicon on Nothing (SON) devices. Advanced control of etching allows getting over the photolithographic limitations; several devices are based upon this gain, for instance Gate-All-Around Field Effect Transistors (GAA FET) [12], Double Gate FET [31] and Fin FET [10].…”

3-D Quantum Numerical Simulation of Transient Response in Multiple-Gate Nanowire MOSFETs Submitted to Heavy Ion Irradiation

“…1) are now widely recognized as one of the most promising solutions for meeting the roadmap requirements in the deca-nanometer scale (Park & Colinge, 2002). A wide variety of architectures, including planar Double-Gate (DG) (Frank et al, 1992;Harrison et al, 2004), Vertical Double-Gate, Triple-Gate (Tri-gate) (Guarini et al, 2001;Park & Colinge, 2002), FinFET (Choi et al, 2001;Kedzierski et al, 2002), Omega-Gate (Ω -Gate) (Park et al, 2001), Pi-Gate (π -Gate) (Yang et al, 2002), ∆-channel SOI MOSFET (Jiao & Salama, 2001), DELTA transistor (Hisamoto et al, 1989), Gate-All-Around (GAA) (Colinge et al, 1990;Park & Colinge, 2002), Rectangular or Cylindrical nanowires www.intechopen.com Numerical Simulations -Applications, Examples and Theory 68 (Jimenez et al, 2004), has been proposed in the literature. These structures exhibit a superior control of short channel effects resulting from an enhanced electrostatic coupling between the conduction channel and the surrounding gate electrode.…”