Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

Badaroglu, Mustafa; Heijningen, M. van; Gravot, V.; Compiet, J.; Donnay, S.; Engels, M.; Gielen, Georges; Man, H. De

doi:10.1109/jssc.2002.803938

Cited by 65 publications

(17 citation statements)

References 17 publications

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“…The peak-to-peak ground noise is a function of the rise time of the current load, parasitic inductance of the ground network, and the decoupling capacitance in the circuit, as specified by (7). Correspondingly, these parameters determine the dominant substrate noise generation mechanism by affecting the number of switching gates at which ground coupling surpasses source/drain coupling.…”

Section: B Effect Of Rise Time Inductance and Capacitance On Dominmentioning

confidence: 99%

“…It is usually assumed in large scale circuits that power/ground coupling dominates source/drain coupling [5], [6], [7]. The validity of this assumption, however, depends upon several circuit parameters, such as the number of simultaneously switching gates, rise time, decoupling capacitance, and parasitic inductance of the power/ground rails.…”

Section: Introductionmentioning

confidence: 99%

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Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates

Salman

Friedman

Secareanu³

et al. 2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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Abstract-The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as compared to SPICE. The regions where ground coupling and source/drain coupling dominate are described based on this model. The impact of multiple parameters such as the rise time, number of switching gates, decoupling capacitance, and parasitic inductance on the dominant noise coupling mechanism is investigated. The dominance of ground coupling in large scale circuits, as generally assumed, is shown to be invalid if sufficient decoupling capacitance is used or the circuit exhibits a low parasitic inductance such as a flip-chip package. The efficacy of several noise reduction techniques is discussed based on the application of the dominant noise analysis model.

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Section: B Effect Of Rise Time Inductance and Capacitance On Dominmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates

Salman

Friedman

Secareanu³

et al. 2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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“…Three approaches have been proposed to manage substrate coupling and power/ground noise; 1) develop design strategies to lower the propagated noise, 2) reduce the noise sensitivity of the circuit, and 3) reduce the magnitude of the noise at the input to lower the noise at the output [1]. The third technique is the primary focus of this paper.…”

Section: Introductionmentioning

confidence: 99%

“…Spreading the switching events of the clock signal in the time domain to reduce the amplitude of the spectral spike at the clock frequency has been proposed [1]. Clock skew optimization to partition the clock into several clock domains is another method to reduce the amplitude of the spectral noise spikes [4]- [6].…”

Section: Introductionmentioning

confidence: 99%

Pseudo-random clocking to enhance signal integrity

Köse

Salman

Ignjatović

et al. 2008

2008 IEEE International SOC Conference

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Abstract-A methodology is proposed to reduce power/ground and substrate coupling noise by randomizing the clock signal. A pseudo-random number generation algorithm is used to produce a pseudo-random clock. A probability adjustment technique is introduced to compensate for the speed loss, permitting the average frequency of the pseudo-random clock to be determined. The proposed method achieves more than 24 dB attenuation in noise at the center frequency at a cost of less than 4% reduction in speed.

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“…A schematic of the macromodel is shown in Figure 4. This macromodel is based on that proposed in [5] with the addition of voltage sources to represent the capacitive sources of noise such as interconnect. The current sources I V DD and I V SS represent the noise in the power and ground lines respectively.…”

Section: B Macromodelmentioning

confidence: 99%