Methods for analysing and improving the fault resilience of delay-insensitive codes

Lechner, Jakob; Steininger, Andreas; Huemer, Florian

doi:10.1109/iccd.2015.7357160

Cited by 4 publications

(4 citation statements)

References 14 publications

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“…The proposed DIRC codes decrease the code rate of 13.15% and 23.25% compared to zero-sum codes with 1-of-2 and 1-of-4 codes, respectively [31]. The DI codes with single parity (SP) and hamming codes (HC) are used to improve fault resilience in asynchronous communication links [32]. The proposed DIRC codes decrease the code rate by 29.93% against SP with 1-of-2 codes and 9.34% against HC with 1-of-4 codes [32].…”

Section: Resultsmentioning

confidence: 99%

“…The DI codes with single parity (SP) and hamming codes (HC) are used to improve fault resilience in asynchronous communication links [32]. The proposed DIRC codes decrease the code rate by 29.93% against SP with 1-of-2 codes and 9.34% against HC with 1-of-4 codes [32]. The fault-tolerant four-phase DI codes mitigate the TFs in asynchronous communication links [33].…”

Section: Resultsmentioning

confidence: 99%

“…Table 3. Code rate analysis of different fault-tolerable codes [30]- [33] with proposed work Coding approach QDI Systematic 1-of-n codes Code rate TRDIC [30] Yes No 1-of-2 0.4 1-of-4 0.5 Zero-Sum [31] No Yes 1-of-2 0.38 1-of-4 0.43 DI with SP [32] No No 1-of-2 0.471 DI with HC [32] No No 1-of-4 0.364 DIC [33] No No 1-of-2 0. TFs.…”

Section: Resultsmentioning

confidence: 99%

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Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

Siddagangappa,

Dunthur Krishnagowda,

Tumkur Srinivas Murthy

2024

IJEECS

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<div align="center"><span>One promising approach for creating the chip-level connection of multiprocessing system on chip (MPSoC) is asynchronous logic. However, asynchronous systems are susceptible to errors. In this manuscript, the efficient fault-tolerant (FT) quasi-delay-insensitive (QDI) pipeline modules are designed using a delay-insensitive redundant check (DIRC) coding mechanism. The DIRC coding approach can tolerate single and multi-bit transient faults (TFs) in QDI-pipeline modules. The 4-phase 1-of-n coding approach incorporates DIRC-based QDI pipeline stages to strengthen the asynchronous links against TFs. The DIRC-based QDI pipeline stages are further used as asynchronous links in asynchronous network-on-chip ((NoC) for fault-free communication. The performance metrics like chip area, delay, and power parameters are evaluated in detail against different data widths for both basic unprotected and DIRC-based QDI pipeline modules. <br /> The DIRC-based QDI-pipeline module with 1-of-4 code uses only <2% chip area with a delay of 7.4 ns and power of 117 mW on Artix-7 chip for data width 128. The code rate of the proposed work decreased by 33.33% for both 1-of-2 and 1-of-4 codes in DIRC-based QDI-pipeline modules.</span></div>

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

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Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

Siddagangappa,

Dunthur Krishnagowda,

Tumkur Srinivas Murthy

2024

IJEECS

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“…Error detection and error correction have not been covered in this paper. If these properties are an issue, the concepts presented in [25,26] can be consulted additionally. In this context, it should also be mentioned that the extra bit encoded by the DS protocol is very robust, which might be advantageous for transmitting specifically sensitive information; for details see [8].…”

Section: Discussionmentioning

confidence: 99%

Novel Approaches for Efficient Delay-Insensitive Communication

Huemer

Steininger

2019

JLPEA

Self Cite

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The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnections instrumental. Delay-insensitive codes are very attractive in this context. There is considerable literature on this topic that classifies delay-insensitive communication channels according to the protocols (return-to-zero versus non-return-to-zero) and with respect to the codes (constant-weight versus systematic), with each solution having its specific pros and cons. From a higher abstraction, however, these protocols and codes represent corner cases of a more comprehensive solution space, and an exploration of this space promises to yield interesting new approaches. This is exactly what we do in this paper. More specifically, we present a novel coding scheme that combines the benefits of constant-weight codes, namely simple completion detection, with those of systematic codes, namely zero-effort decoding. We elaborate an approach for composing efficient “Partially Systematic Constant Weight” codes for a given data word length. In addition, we explore cost-efficient and orphan-free implementations of completion detectors for both, as well as suitable encoders and decoders. With respect to the protocols, we investigate the use of multiple spacers in return-to-zero protocols. We show that having a choice between multiple spacers can be beneficial with respect to energy efficiency. Alternatively, the freedom to choose one of multiple spacers can be leveraged to transfer information, thus turning the original return-to-zero protocol into a (very basic version of a) non-return-to-zero protocol. Again, this intermediate solution can combine benefits from both extremes. For all proposed solutions we provide quantitative comparisons that cover the whole relevant design space. In particular, we derive coding efficiency, power efficiency, as well as area effort for pipelined and non-pipelined communication channels. This not only gives evidence for the benefits and limitations of the presented novel schemes—our hope is that this paper can serve as a reference for designers seeking an optimized delay-insensitive code/protocol/implementation for their specific application.

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