Micro-architecture independent analytical processor performance and power modeling

Steen, Sam Van den; Pestel, Sander De; Mechri, Moncef; Eyerman, Stijn; Carlson, Trevor E.; Black-Schaffer, David; Hägersten, Erik; Eeckhout, Lieven

doi:10.1109/ispass.2015.7095782

Cited by 30 publications

(13 citation statements)

References 63 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They achieve good speedups with minimal loss in accuracy for both performance and power estimations. In addition, [35] demonstrated an analytical performance and power model, based on micro-architecture-independent application profiles to enable the evaluation of large design spaces using a single application-specific but architectureindependent profile.…”

Section: Related Workmentioning

confidence: 99%

A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors

Yasin

Haj-Yahya

Ben-Asher

et al. 2019

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

The slowdown in technology scaling puts architectural features at the forefront of the innovation in modern processors. This article presents a Metric-Guided Method (MGM) that extends Top-Down analysis with carefully selected, dynamically adapted metrics in a structured approach. Using MGM, we conduct two evaluations at the microarchitecture and the Instruction Set Architecture (ISA) levels. Our results show that simple optimizations, such as improved representation of CISC instructions, broadly improve performance, while changes in the Floating-Point execution units had mixed impact. Overall, we report 10 architectural insights-at the microarchitecture, ISA, and compiler fronts-while quantifying their impact on the SPEC CPU benchmarks.

show abstract

Section: Related Workmentioning

confidence: 99%

A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors

Yasin

Haj-Yahya

Ben-Asher

et al. 2019

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…Compared to detailed simulation, the proposed MLP model achieves an average absolute error of 3.6% for predicting the total time waiting for main memory for a superscalar processor (with a stride-based prefetcher) 1 . This is a significant improvement over prior work with a 16.9% average error [10].…”

Section: Introductionmentioning

confidence: 72%

Modeling Superscalar Processor Memory-Level Parallelism

Steen

Eeckhout

2018

IEEE Comput. Arch. Lett.

Self Cite

View full text Add to dashboard Cite

This paper proposes a analytical model to predict Memory-Level Parallelism (MLP) in a superscalar processor. We profile the workload once and measure a set of distributions to characterize the workload's inherent memory behavior. We subsequently generate a virtual instruction stream, over which we then process an abstract MLP model to predict MLP for a particular micro-architecture with a given ROB size, LLC size, MSHR size and stride-based prefetcher. Experimental evaluation reports an improvement in modeling error from 16.9% for previous work to 3.6% on average for the proposed model.

show abstract

“…With analytical modeling, system's behavior is modeled using mathematical equations. Analytical modeling employs less effort to model a complex system [35], but it does not refer to design decisions and implementation issues that a designer may encounter. It involves assumptions and simplifications that yield quick results.…”

Section: System-level Performance Modeling Techniquesmentioning

confidence: 99%

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Haririan

2020

Computers

View full text Add to dashboard Cite

Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today’s complex embedded designs is a big challenge. Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase. Virtual prototypes of systems prepared through architectural simulation provide a means of evaluating non-existing systems with more flexibility and minimum cost. Efficient interplay between power and performance is a key feature within virtual platforms. This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation. With advent of new computing paradigms and modern application domains with strict resource demands, DVFS and its efficient hardware-managed solutions get even more highlighted. This is mainly because they can react faster to resource demands and thus reduce induced overhead. To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.

show abstract

Micro-architecture independent analytical processor performance and power modeling

Cited by 30 publications

References 63 publications

A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors

A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors

Modeling Superscalar Processor Memory-Level Parallelism

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Contact Info

Product

Resources

About