Micro-architecture independent branch behavior characterization

Pestel, Sander De; Eyerman, Stijn; Eeckhout, Lieven

doi:10.1109/ispass.2015.7095792

Cited by 8 publications

(14 citation statements)

References 13 publications

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“…To achieve this, we have to predict the number of branch mispredictions, cache miss rates and MLP. Predicting the number of branch mispredictions is achieved through a metric called linear branch entropy which captures the (un)predictability of branch instructions [22]. For predicting cache miss rates we collect a reuse distance distribution which is transformed into a stack distance distribution using StatStack [28].…”

Section: Discussionmentioning

confidence: 99%

“…Het aantal sprongmissers voorspellen we aan de hand van een metriek die lineaire sprongentropie genoemd wordt. Deze metriek modelleert de (on)voorspelbaarheid van spronginstructies en laat toe de nauwkeurigheid van een sprongvoorspeller te schatten [22]. Het voorspellen van cachemissers gebeurt door het profileren van een distributie van hergebruiksafstanden.…”

Section: Dankwoordunclassified

“…We explain the different modifications introduced to improve its accuracy. Furthermore, we show how branch misprediction rates can be calculated without simulating the branch predictor [22] and how we predict power consumption using activity factors.…”

Section: Thesis Overviewmentioning

confidence: 99%

“…To achieve this, we rely on a metric called linear branch entropy [22] 3 . The reason why branches can be predicted is that, in general, they are executed many times and branch outcomes are often correlated.…”

Section: Branch Predictor Modelingmentioning

confidence: 99%

“…The average branch entropy needs to be transformed into a number of branch mispredictions. In order to achieve this, De Pestel et al [22] propose a framework to build a model that connects branch entropy to branch misprediction rates for specific branch predictors. This framework is schematically shown in Figure 3.8.…”

Section: Branch Predictor Modelingmentioning

confidence: 99%

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Micro-architecture independent analytical processor performance and power modeling

Steen

Pestel

Mechri

et al. 2015

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Section: Discussionmentioning

confidence: 99%

Section: Dankwoordunclassified

Section: Thesis Overviewmentioning

confidence: 99%

Section: Branch Predictor Modelingmentioning

confidence: 99%

Section: Branch Predictor Modelingmentioning

confidence: 99%

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Micro-architecture independent analytical processor performance and power modeling

Steen

Pestel

Mechri

et al. 2015

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Sabu,

Liu,

Carlson

2024

IEEE Access

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Pre-silicon performance evaluation is a crucial component of computer systems research and development. While simulation has long been the de facto standard in this context, it can be prohibitively time-consuming for long-running, realistic workloads. To expedite this process, researchers have traditionally turned to sampling techniques. However, these techniques typically rely on fixed-length intervals for analysis, which can often be out of sync with the periodicity of program execution. Additionally, since an application's phase behavior is strongly correlated to the code it executes, it can exhibit a hierarchy of phase behaviors that can be observed at various interval lengths, rendering conventional sampling techniques inadequate. To address these limitations, we propose Viper -a novel sampled simulation methodology that applies to single-threaded and multi-threaded workloads by leveraging the hierarchical structure of program execution. Viper takes into account both application periodicity and inter-thread synchronization in order to achieve better sampling accuracy and smaller regions, which enables faster register-transfer level (RTL) simulations. We evaluate Viper with the multi-threaded SPEC CPU2017 benchmarks and demonstrate a significant simulation speedup (up to 2,710×, 358× on average for the train input set) while maintaining an average sampling error of just 1.32%.

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RPPM: Rapid Performance Prediction of Multithreaded Workloads on Multicore Processors

Pestel

Steen

Akram

et al. 2019

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Analytical performance modeling is a useful complement to detailed cycle-level simulation to quickly explore the design space in an early design stage. Mechanistic analytical modeling is particularly interesting as it provides deep insight and does not require expensive offline profiling as empirical modeling. Previous work in mechanistic analytical modeling, unfortunately, is limited to single-threaded applications running on single-core processors. This work proposes RPPM, a mechanistic analytical performance model for multi-threaded applications on multicore hardware. RPPM collects microarchitecture-independent characteristics of a multi-threaded workload to predict performance on a previously unseen multicore architecture. The profile needs to be collected only once to predict a range of processor architectures. We evaluate RPPM's accuracy against simulation and report a performance prediction error of 11.2% on average (23% max). We demonstrate RPPM's usefulness for conducting design space exploration experiments as well as for analyzing parallel application performance.

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Micro-architecture independent branch behavior characterization

Cited by 8 publications

References 13 publications

Micro-architecture independent analytical processor performance and power modeling

Micro-architecture independent analytical processor performance and power modeling

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

RPPM: Rapid Performance Prediction of Multithreaded Workloads on Multicore Processors

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