2011
DOI: 10.5104/jiepeng.4.73
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Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

Abstract: PoP (Package on Package) structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used.Since the logic chips of mobile applications use a pad pitch of less than 80 μm or less, an ultra-fine-pitch flip chip interconnection technique is requir… Show more

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Cited by 24 publications
(3 citation statements)
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“…This test vehicle is designed for direct landing of the copper pillars on substrate interconnect traces without any landing pad. The so-called bump-on-trace (BOT) is expected to advance the interconnect density in contrast to conventional bump-on-pad [9][10]. Assembly of the copper pillars will be conducted using an automated Datacon placement machine capable of dispensing NCP as well as thermal compression bonding of the chips upon placement as desired.…”
Section: Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…This test vehicle is designed for direct landing of the copper pillars on substrate interconnect traces without any landing pad. The so-called bump-on-trace (BOT) is expected to advance the interconnect density in contrast to conventional bump-on-pad [9][10]. Assembly of the copper pillars will be conducted using an automated Datacon placement machine capable of dispensing NCP as well as thermal compression bonding of the chips upon placement as desired.…”
Section: Methodsmentioning
confidence: 99%
“…Despite the obvious benefits, the technology as it stands today has several issues for full implementation particularly at the finer pitch level [9][10]. Noted disadvantages are: manufacturing cost, reliability of less robust interconnects [9], high aspect ratio wafer level plating, die to substrate misregistration, die coplanarity, substrate warpage, tearing of copper pillar bumps due to imposed stresses, and production of high density interconnect substrate as well as handling of thinner wafers for further package miniaturization.…”
Section: Introductionmentioning
confidence: 97%
“…At the same time, fabrication cost and the environmental impact of employed processes must be driven down. With regard to circuit formation for semiconductors and packaging, some trends in fabrication that reflect this situation are, for example, development of through silicon vias and copper post connection for stacked chip devices and three-dimensional large-scale integration, transition of subtractive aluminum to damascene , at the wafer level, and development of build-up construction, multilayer substrates, and subtractive to semiadditive methods for patterning at the substrate level. In order to implement frontier construction techniques, development of direct patterning and fully additive metallization technology provides a powerful tool that can satisfy future demands and prerequisites.…”
Section: Introductionmentioning
confidence: 99%