Microarchitecture of Network-on-Chip Routers

Dimitrakopoulos, Giorgos; Ψαρράς, Αναστάσιος; Seitanidis, Ioannis

doi:10.1007/978-1-4614-4301-8

Cited by 35 publications

(36 citation statements)

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“…Alternatively the elastic buffer (EB) is the most primitive form of a register (or buffer) that implements the ready/valid handshake protocol [17]. The EB at the sender implements a dual interface; it accepts new data from its internal logic and transfers the available data to the link as shown in figure 2, when the valid and ready signals are both equal to logic high, so an EB can be built around a FIFO queue.…”

Section: B Elastic Buffer Fifo Modelmentioning

confidence: 99%

Design of a dynamic depth high-throughput multi-clock FIFO for the DSPIN

Kamal

Aróstegui

2015

2015 1st International Conference on Next Generation Computing Technologies (NGCT)

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The clock distribution within ChipMultiprocessors(CPMs) and System-on-chips (SoCs) come to be difficult as the number of processing elements increasing and the communication between those components are becoming even more critical. In recent years, researchers proposed Globally Synchronous Locally Synchronous (GALS) clocking scheme to reduce clock skew, power, and energy consumption in CPMs and SoCs. In this paper we have demonstrated dynamic depth multi-synchronous first-in first-out (FIFO) buffer which is useful for transferring data between two processing elements within a Distributed Scalable Predictable Interconnect Network(DSPIN).It also demonstrates dynamic calculation of FIFO depth using two clock frequency and packet size of in coming data.

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Section: B Elastic Buffer Fifo Modelmentioning

confidence: 99%

Design of a dynamic depth high-throughput multi-clock FIFO for the DSPIN

Kamal

Aróstegui

2015

2015 1st International Conference on Next Generation Computing Technologies (NGCT)

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“…To reduce the transmission delay, some parts of stages are arranged in parallel. In typical NoC architectures [16]- [19], the RC step (that calculates the destined output port based on the destination information in a header flit) is arranged with other steps to provide the lookahead routing.…”

Section: Cellular Automaton Modeling Of Rtl Nocmentioning

confidence: 99%

Fast and Cycle-Accurate Simulation of RTL NoC Designs Using Test-Driven Cellular Automata

et al. 2020

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Speeding up the register-transfer level (RTL) simulation of network-on-chip (NoC) is essential for design optimization under various use scenarios and parameters. One of the promising approaches for RTL NoC speedup is high-level modeling. Conventional high-level modeling approaches lead to an accuracy problem or modeling efforts that are caused by the absence of modeling framework or requiring in-depth knowledge of specific behaviors of target NoCs. To support cycle-accurate and formal high-level modeling framework, we propose a cellular automata (CA) modeling framework for RTL NoC. The CA abstracts detailed RTL NoC dynamics into the proposed high-level state transitions, which support flit transmission among CA components through dynamically changing flit paths based on the target RTL routing and arbitration algorithms. To prevent the meaningless execution of stable CA, the CA are designed to be triggered by state-change events. The proposed simulation engine asynchronously invokes CA to update their states and perform actions of flit transmissions or flit-path changes based on the state-decision result. To reduce the modeling difficulty, we provide a test environment that generates the state-transition rules for CA after monitoring the relationships between high-level states and leading actions under randomly injected packets during target RTL NoC simulations. Experiments demonstrate cycle-level functional homogeneity between RTL and the abstracted CA NoC models and significant simulation speedup. INDEX TERMS Network on chip, cellular automata, RTL design, test-driven rule generation, event-based simulation. FIGURE 2. Examples of CA network and BC mappings.

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“…Each input port need an HT, so there are totally five main HTs and five sinkhole launchers, and each sinkhole launcher is synchronized with its pairing main HT through a control signal. For more details at circuit level, the HT's insertion of one port in a single-cycle VC-based router [37] is shown in Fig. 4.…”

Section: Ht Designs For Sinkhole/blackhole Attacksmentioning

confidence: 99%

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

Zhang

Wang

Jiang

et al. 2018

Journal of Systems Architecture

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There are ample opportunities at both design and manufacturing phases to meddle in a many-core chip system, especially its underlining communication fabric, known as the networks-on-chip (NoC), through the inclusion of malicious hardware Trojans (HT). In this paper, we focus on studying two specific HT-assisted Denial-of-Service (DoS) attacks, namely the sinkhole and blackhole attacks, that directly target the NoC of a many-core chip. As of the blackhole attacks, those intermediate routers with inserted HTs can stop forwarding data packets/flits towards the packets' destination; instead, packets are either dropped from the network or diverted to some other malicious nodes. Sinkhole attacks, which exhibit similar attack effects as blackhole attacks, can occur when the NoC supports adaptive routing. In this case, a malicious node actively solicits packets from its neighbor nodes by pretending to have sufficient free buffer slots. Effects and efficiencies of both sinkhole and blackhole DoS attacks are modeled and quantified in this paper, and a few factors that influence attack effects are found to be critical. Through fine-tuning of these parameters, both attacks are shown to cause more damages to the NoC, measured as over 30% increase in packet loss rate. Even with current detection and defense methods in place, the packet loss rate is still remarkably high, suggesting the need of new and more effective detection and defense methods against the enhanced blackhole and sinkhole attacks as described in the paper.

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Microarchitecture of Network-on-Chip Routers

Cited by 35 publications

References 0 publications

Design of a dynamic depth high-throughput multi-clock FIFO for the DSPIN

Design of a dynamic depth high-throughput multi-clock FIFO for the DSPIN

Fast and Cycle-Accurate Simulation of RTL NoC Designs Using Test-Driven Cellular Automata

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

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