Microprocessors — 10 Years Back, 10 Years Ahead

Sohi, Gurindar S.

doi:10.1007/3-540-44577-3_14

Cited by 9 publications

(4 citation statements)

References 21 publications

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“…The latency gap between the processor and its memory doubles approximately every six years, and an increasing part of the processor's time is spent on waiting for the completion of memory operations [8]. Matching the performances of the processor and the memory is an increasingly difficult task [9].…”

Section: Introductionmentioning

confidence: 99%

Modeling and Analysis of Dual Block Multithreading

Zuberek

2004

Lecture Notes in Computer Science

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Instruction level multithreading is a technique for tolerating longlatency operations (e.g., cache misses) by switching the processor to another thread instead of waiting for the completion of a lengthy operation. In block multithreading, context switching occurs for each initiated long-latency operation. However, processor cycles during pipeline stalls as well as during context switching are not used in typical block multithreading, reducing the performance of a processor. Dual block multithreading introduces a second active thread which is used for instruction issuing whenever the original (main) thread becomes inactive. Dual block multithreading can be regarded as a simple and specialized case of simultaneous multithreading when two (simultaneous) threads are used to issue instructions for a single pipeline. The paper develops a simple timed Petri net model of a dual block multithreading and uses this model to estimate the performance improvements of the proposed dual block multithreading.

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Section: Introductionmentioning

confidence: 99%

Modeling and Analysis of Dual Block Multithreading

Zuberek

2004

Lecture Notes in Computer Science

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“…Sohi [131] expects that the distinction between the SMT and CMP microarchitectures is likely to be blurred over time, as we have already seen for the implicit multithreading approaches above. Increasing wire delays will require decentralization of critical processor functionality favouring CMP, while flexible resource allocation policies will enhance resource sharing as in SMT.…”

Section: Discussionmentioning

confidence: 91%

“…In either case, multithreaded processors will logically appear to be collections of processing elements with additional support for speculative execution. Thus, in addition to executing parallel threads, the logical processors could execute single programs that are divided into speculative threads [131].…”

Section: Discussionmentioning

confidence: 99%

Multithreaded Processors

Ungerer¹

2002

The Computer Journal

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The instruction-level parallelism found in a conventional instruction stream is limited. Studies have shown the limits of processor utilization even for today's superscalar microprocessors. One solution is the additional utilization of more coarse-grained parallelism. The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance. The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip. In contrast, the multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline. Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor. The execution units are multiplexed between the threads in the register sets. Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple threads each cycle. Simultaneous multithreaded processors combine the multithreading technique with a wideissue superscalar processor such that the full issue bandwidth is utilized by potentially issuing instructions from different threads simultaneously. This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.

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“…Speculative Multi-Threading (SpMT) is a promising approach to extract Thread Level Parallelism (TLP) out of sequential programs in this way. There have been plenty of attempts to design SpMT architectures [15] [16] [17].…”

Section: A Spmt With Code Block Reorderingmentioning

confidence: 99%

Core affinity code block schedule to reduce inter-core data synchronization of SpMT

zjutoe¹

2022

Preprint

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Extract parallelism from programs is growing important as the number of cores of processors is increasing. Parallelization usually involves splitting a sequential thread, and schedule the split code to run on multiple cores. E.g. Some previous Speculative Multi-Threading research used code block reordering to automatically parallelize a sequential thread on multi-core processors. Although the parallelized code blocks can run on different cores, there may still be some data dependences among them. Therefore such parallelization will introduce data dependences among the cores where the code blocks run, which should be resolved alongside the execution by cross-core data sync. Cross-core data sync is usually expensive. This paper proposes to minimize the cross-core data sync with core affinity aware code block scheduling. Our work is based on an Speculative Multi-Threading (SpMT) approach with code block reordering. We improve it by implementing an affinity aware block scheduling algorithm. We built a simulator to model the SpMT architecture, and conducted experiments with SPEC2006 benchmarks. The data shows that plenty of cross-core data sync could be reduced (e.g. Up to 28.7% for gromacs) by the affinity aware block scheduling. For inter-core register sync delay of 5 cycles, this may suggest 3.73% increase in performance.

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Microprocessors — 10 Years Back, 10 Years Ahead

Cited by 9 publications

References 21 publications

Modeling and Analysis of Dual Block Multithreading

Modeling and Analysis of Dual Block Multithreading

Multithreaded Processors

Core affinity code block schedule to reduce inter-core data synchronization of SpMT

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