MicroSPARC: a case-study of scan based debug

Holdbrook, K.; Joshi, Shrinivas; Mitra, S.; Petolino, J.; Raman, Raghavan; Wong, M.W.T.

doi:10.1109/test.1994.527937

Cited by 31 publications

(10 citation statements)

References 3 publications

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“…Then scan dump can take place to get the internal states inside the chip. In [13], some scan-based debug methodologies are presented. The debugging related features include TAP, full scan design for all flips-flops, clock controller that enables scan-based control and so on.…”

Section: Related Workmentioning

confidence: 99%

A New Post-Silicon Debug Approach Based on Suspect Window

Gao

Han

2009

2009 27th IEEE VLSI Test Symposium

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-Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.

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Section: Related Workmentioning

confidence: 99%

A New Post-Silicon Debug Approach Based on Suspect Window

Gao

Han

2009

2009 27th IEEE VLSI Test Symposium

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“…Manufacturing test to detect hard errors is a well-understood topic [12], although fault debug and isolation is an active research area. Schuchmann and Vijaykumar [4] and Holdbrook et al [39] propose altering the microarchitecture to increase visibility of scan. Schuchmann suggests increasing intercycle independence of core structures to isolate faults within two successive pipeline stages.…”

Section: Related Workmentioning

confidence: 99%

Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors

Khan

Kundu

2011

IEEE Trans. Dependable and Secure Comput.

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As the semiconductor industry continues its relentless push for nano-CMOS technologies, long-term device reliability and occurrence of hard errors have emerged as a major concern. Long-term device reliability includes parametric degradation that results in loss of performance as well as hard failures that result in loss of functionality. It has been reported in the ITRS roadmap that effectiveness of traditional burn-in test in product life acceleration is eroding. Thus, to assure sufficient product reliability, fault detection and system reconfiguration must be performed in the field at runtime. Although regular memory structures are protected against hard errors using error-correcting codes, many structures within cores are left unprotected. Several proposed online testing techniques either rely on concurrent testing or periodically check for correctness. These techniques are attractive, but limited due to significant design effort and hardware cost. Furthermore, lack of observability and controllability of microarchitectural states result in long latency, long test sequences, and large storage of golden patterns. In this paper, we propose a low-cost scheme for detecting and debugging hard errors with a fine granularity within cores and keeping the faulty cores functional, with potentially reduced capability and performance. The solution includes both hardware and runtime software based on codesigned virtual machine concept. It has the ability to detect, debug, and isolate hard errors in small noncache array structures, execution units, and combinational logic within cores. Hardware signature registers are used to capture the footprint of execution at the output of functional modules within the cores. A runtime layer of software (microvisor) initiates functional tests concurrently on multiple cores to capture the signature footprints across cores to detect, debug, and isolate hard errors. Results show that using targeted set of functional test sequences, faults can be debugged to a fine-granular level within cores. The hardware cost of the scheme is less than three percent, while the software tasks are performed at a high-level, resulting in a relatively low design effort and cost.Index Terms-Chip Multiprocessor (CMP), hard error detection, isolation and tolerance, hardware/software codesign.

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“…One straight-forward approach is to use the existing scan-chains to capture the state of the system at a given time [1]. While it is cost-effective, as scanchains are present to enable manufacturing test, it is intrusive, as the system must be stopped.…”

Section: Related Workmentioning

confidence: 99%

A distributed architecture to check global properties for post-silicon debug

Larsson¹,

Vermeulen

Goossens

2010

2010 15th IEEE European Test Symposium

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Abstract-Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations.

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MicroSPARC: a case-study of scan based debug

Cited by 31 publications

References 3 publications

A New Post-Silicon Debug Approach Based on Suspect Window

A New Post-Silicon Debug Approach Based on Suspect Window

Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors

A distributed architecture to check global properties for post-silicon debug

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