Minimization of CNTFET Ternary Combinational Circuits Using Negation of Literals Technique

Sridevi, V.; Jayanthy, T.

doi:10.1007/s13369-014-1147-y

Cited by 30 publications

(23 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The transistor count comparison for the proposed STI, TNAND and TNOR with various existing designs demonstrates a notable reduction in the number of transistors. For STI, around 50% reduction in number of transistors is observed compared to STI in [7], [34], [38]- [40] and around 40% compared to STI in [44]. For TNAND, around 50% compared to [7], [34], [38], [40], [44] and around 37.5% compared to [39] is observed.…”

Section: Resultsmentioning

confidence: 91%

“…For STI, around 50% reduction in number of transistors is observed compared to STI in [7], [34], [38]- [40] and around 40% compared to STI in [44]. For TNAND, around 50% compared to [7], [34], [38], [40], [44] and around 37.5% compared to [39] is observed. For the case of TNOR, around 50% compared to [7], [34], [38], [40] and around 37.5% compared to [39].…”

Section: Resultsmentioning

confidence: 91%

“…For TNAND, around 50% compared to [7], [34], [38], [40], [44] and around 37.5% compared to [39] is observed. For the case of TNOR, around 50% compared to [7], [34], [38], [40] and around 37.5% compared to [39]. Similarly, for the case of ternary arithmetic circuits the comparison of transistor count is shown in Table 12.…”

Section: Resultsmentioning

confidence: 95%

“…The THA implemented using the proposed CNTFET-RRAM ternary logic gates shows a notable reduction in transistor count. Around 33.82%, 19.64%, 65.11%, −5.55%, compared to THA in [7], [38], [40], [44] respectively, while the transistor count compared to [45] remains the same. For THS, the transistor count is reduced by around 65.11% compared to the design in [40].…”

Section: Resultsmentioning

confidence: 96%

“…A ternary half subtractor shown in Fig. 9 is a combinational logic circuit that subtracts one bit from the other and generates two outputs difference and borrow with output equations given by [40]: where A p and B p represent the output to A and B inputs from the decoder shown in Fig. 7.…”

Section: Figurementioning

confidence: 99%

See 4 more Smart Citations

Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits

et al. 2020

View full text Add to dashboard Cite

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations. INDEX TERMS Multiple valued logic (MVL), ternary logic systems, emerging technologies, carbon nanotube field effect transistor (CNTFET), resistive random access memory (RRAM).

show abstract