MMSE equalization for forward link in 3G CDMA: symbol-level versus chip-level

Krauss, T.P.; Hillery, W.J.; Zoltowski, M.D.

doi:10.1109/ssap.2000.870073

Cited by 34 publications

(13 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Because of the spatial multiplexing employed in the system, the transmit beamforming filters h' Z for all entries of sk, i.e., m = 1, .... RG, are the RG eigenvectors corresponding to the RG largest eigenvalues of the matrix Zk in (8).…”

Section: Coordinated Interference-aware Beamformingmentioning

confidence: 99%

“…The proposed technique, similar to Coordinated Interference-aware Beamforming (CIB), for flat-fading channels [5] and [6], can provide means to schedule multiple users to be active. Chip-level receivers are well understood and discussed in [7], [8], [9]. Effective chip-level equalization aims at restoring synchronism and orthogonality amongst the active users.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Chip-Level Coordinated Interference-Aware Beamforming for MIMO-CDMA in Frequency-Selective Broadcast Channels

Salehi

2007

2007 41st Annual Conference on Information Sciences and Systems

View full text Add to dashboard Cite

In this paper a linear multi-user beamforming technique is proposed for frequency-selective channels in MultipleInput-Multiple-Output (MIMO) Wideband Code Division Multiple Access (WCDMA) system. Assuming perfect Channel State Information (CSI) is available at both transmitter and receiver, transmit beamforming and receive beamforming are coordinated to mitigate multi-user, multiple access (MAI), and Inter-Chip Interference (ICI) by maximizing an approximate lower bound of each individual Signal to Interference and Noise Ratio (SINR). Chip-level equalization is selected to mitigate the ICI due to its low computational complexity. Simulation results indicate that this technique outperforms traditional linear techniques in approaching high receive SINR, thus achieving higher data rates and/or lower error rates in large interference cases.

show abstract

Section: Coordinated Interference-aware Beamformingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Chip-Level Coordinated Interference-Aware Beamforming for MIMO-CDMA in Frequency-Selective Broadcast Channels

Salehi

2007

2007 41st Annual Conference on Information Sciences and Systems

View full text Add to dashboard Cite

show abstract

“…In [3], we compared the performance of a chip-level equalizer and a symbol-level equalizer similar to the type presented in [5] and derived without the long code in [2].…”

Section: Introductionmentioning

confidence: 99%

Comparative performance evaluation of three MMSE equalizers for the CDMA forward link in frequency selective multipath

Zoltowski

Hillery²,

Krauss³

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)

Self Cite

View full text Add to dashboard Cite

We derive a subspace constrained "symbol-level '' equalizer for the CDMA downlink over a frequency selective multipath channel and compare its performance with the chiplevel equalizer; the unconstrained symbol-level equalizer; and the RAKE receivel: The constrained equalizer must lie in a subspace determined by shifred versions of the user's Walsh-Hadamard code multiplied by the long code. Due to the presence of the long code, the Constrained equalizer varies from symbol to symbol, as the symbol-level equalizer does. Since the symbol is being estimated directly, the constrained equalizer performs better than the chip-level equalizer but at the expense of greatly increased computational complexity. The unconstrained equalizer performs better than the subspace constrained equalizer and is computationally less demanding. We summarize the advantages and disadvantages of each equalizel:

show abstract

“…The Rake receiver is shown to provide unacceptable performance in such systems as HSDPA because of the short spreading gain. To achieve a good tradeoff between the performance and complexity, Linear-Minimum-Mean-Square-Error (LMMSE) based chip level equalization has been proposed as one of the most promising sub-optimal receivers [1,2,3]. System capacity of the HSDPA system is significantly increased because the orthogonality of the spreading codes is partially restored by the equalization.…”

Section: Introductionmentioning

confidence: 99%

Scalable FPGA architectures for LMMSE-based SIMO chip equalizer in HSDPA downlink

Guo

McCain

Zhang

et al.

The Thrity-Seventh Asilomar Conference on Signals, Systems &Amp; Computers, 2003

View full text Add to dashboard Cite

Abstract-In this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink receivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz structure of the correlation matrix. A PipelinedMultiplexing-Scheduler (PMS) is designed in the front-end to achieve scalable computation of the correlation coefficients. Very efficient VLSI architectures are designed by investigating the multiple level parallelism and pipelining with a Precision-C based High-Level-Synthesis (HLS) design methodology. A 1× × × ×2 Single-Input-Multiple-Output (SIMO) downlink receiver is designed and integrated in the HSDPA prototype system with Xilinx Virtex-II XC2V6000 FPGAs. The design demonstrates more area/time efficiency by achieving the best tradeoffs between the usage of functional units and real-time requirements.

show abstract

MMSE equalization for forward link in 3G CDMA: symbol-level versus chip-level

Cited by 34 publications

References 8 publications

Chip-Level Coordinated Interference-Aware Beamforming for MIMO-CDMA in Frequency-Selective Broadcast Channels

Chip-Level Coordinated Interference-Aware Beamforming for MIMO-CDMA in Frequency-Selective Broadcast Channels

Comparative performance evaluation of three MMSE equalizers for the CDMA forward link in frequency selective multipath

Scalable FPGA architectures for LMMSE-based SIMO chip equalizer in HSDPA downlink

Contact Info

Product

Resources

About