Modeling and Analysis of Drift-Cancellation Techniques for Time-Based Integrated Resistive Sensor Interfaces

Marin, Jorge; Sacco, Elisa; Vergauwen, Johan; Gielen, Georges

doi:10.1109/tcpmt.2018.2849682

Cited by 4 publications

(6 citation statements)

References 20 publications

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“…Using ( 6) and ( 9)-( 12), the expression for the final digital output, D_out, can be written as (13).…”

Section: Interfacing With a Wheatstone Bridgementioning

confidence: 99%

“…where k ADC is the gain of the ADC, f CLK_NCO is the frequency of Clk_NCO, and N PA is the number of bits of the phase accumulator register. If this architecture is interfaced with a full Wheatstone bridge resistive sensor, the expression for the final digital output will be the same as (13). This makes the output independent of the supply voltage and ADC parameters, which are susceptible to drift, making it more suitable to be used in harsh environments.…”

Section: Architecture-2mentioning

confidence: 99%

“…A closed-loop Wheatstone bridge sensor readout architecture that works on the concept of balancing the bridge was presented in [12], which suppresses possible supply drifts, but its application is limited to half-bridge structures and the accuracy highly depends on the matching between the two VCOs. Since the VCO operates over a small input range in a closed loop architecture, the system gain error due to the VCO drift is automatically reduced [13]. Nevertheless, the gain drift of the involved digital-to-analog converter (DAC) in the loop has a direct impact on the system gain error, and the mismatch between the two VCOs is still an issue.…”

Section: Introductionmentioning

confidence: 99%

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Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

et al. 2023

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Maintaining the accuracy of a sensor system across various operating conditions has always been a challenge, especially for those operating in harsh surroundings such as a radiation environment. Concerning frequency-based sensor interfaces, supply voltage drifts and gain shift of the voltage-to-frequency converter (VFC) are critical design issues. These manifest as gain, offset, and linearity errors at the system level and therefore require continuous correction mechanisms. In this paper, dynamic gain and offset error-compensated open-loop frequency-based sensor interface architectures with adaptive clock frequency are proposed, which result in a ratiometric digital output. To address the mismatch issue, two architectures, one with periodic swapping of the VFCs’ inputs and outputs, and the other with the use of a single analog-to-digital converter (ADC) as an analog front end, are developed. The concepts were demonstrated with implementations on a Zynq board (ZYBO). The results of the first architecture showed that for a 25% gain mismatch between the VFCs, the output gain error was reduced from around 7.4% to 0.79% and the offset error was reduced from around 11.8% to 0.01%. Additionally, for the second architecture, a maximum of 0.11% gain error and 0.1% offset error were recorded for an emulated ±25% supply drift.

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“…Using ( 6) and ( 9)-( 12), the expression for the final digital output, D_out, can be written as (13).…”

Section: Interfacing With a Wheatstone Bridgementioning

confidence: 99%

Section: Architecture-2mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

et al. 2023

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“…For this reason, a configurable threshold is a key point to make the gate driver universal. The stability and parameter drift over time of electronic components, such as sensors, which are used in critical sub-systems in aerospace applications and operate in harsh environments has been intensively studied (Marin et al, 2018). In addition, any integrated circuit is subject to manufacturing process variation that makes its performance different from simulation results.…”

Section: System Requirementsmentioning

confidence: 99%

A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology

Aimaier²,

Alameh

et al. 2020

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)

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En raison de vitesses de commutation plus élevées, de faible résistance à l'état passant et de taille miniaturisée en comparaison avec des contreparties en silicium, l'utilisation de transistors de puissance à base de nitrure de gallium (GaN) est de plus en plus courante dans les circuits de puissances modernes. Avec des figures de mérite supérieures, les convertisseurs de puissance utilisant des dispositifs GaN peuvent fonctionner à des fréquences de commutation élevées. Cela se traduit par des dimensions plus petites, une efficacité supérieure et une réduction du coût du système. La redondance et la reconfigurabilité sont souhaitables dans les applications critiques pour la sécurité telles que les systèmes automobiles et aérospatiaux. Ces derniers fonctionnent dans des conditions difficiles nécessitant un niveau élevé de flexibilité et une grande fiabilité. Ce mémoire présente un circuit de pilotage de grille pour un tel système d'alimentation reconfigurable. Destiné à être au coeur d'un système d'alimentation haute tension (HT) programmable et flexible, le pilote de grille présenté dans ce travail est capable de commander une large gamme de dispositifs GaN de différentes tailles. Cela est accompli en ayant un mécanisme configurable de vitesse de mis-à-on et mis-à-off. Cette fonctionnalité élimine le besoin de résistances de grille discrètes. Elle permet donc des conceptions de circuits plus denses, telles que l'intégration de système dans un boîtier (SiP-system-in-package). Dans un tel système les pilotes de grille, les dispositifs GaN et d'autres circuits intégrés de commande sont placés sur le même interposeur. La vitesse configurable de mis-à-on et de mis-à-off reconfigurable permet également de réduire les interférences électromagnétiques (EMI). Cela est important dans les applications critiques pour la sécurité. Une structure uniforme d'unités de commutation en demi-pont est proposée. Cette dernière permet une reconfigurabilité du fonctionnement du système avec une variété de topologies possibles à l'aide d'un grand nombre de cellules de commutation. Le pilote de grille exige un circuit de décalage de niveau de 200 V intégré. Ce circuit utilise une technique d'annulation de bruit en mode commun, ayant fait l'objet d'une étude approfondie. En utilisant cette technique dans une technologie HT SOI (silicium sur isolant), une immunité à une variation de bruit (CMTI) de 80 V/ns est obtenue. Le pilote de grille a un temps mort configurable allant de 5 ns à 60 ns. Ce temps mort configurable minimise les pertes dues à la conduction par mécanisme de «diode de corps» des transistors GaN pendant la période de conduction en roue libre pour différents profils de charge. Toutes les configurations sont programmées à travers un registre à décalage. Le circuit de pilotage de grille a été fabriqué avec le procédé SOI de 200-V 0,18-μm (XFAB XT018). Les résultats expérimentaux montrent que la puce peut piloter les transistors GaN ciblés de la plus petite à la plus grande taille aux vitesses de mis-à-on et mis-à-off souhaitée...

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“…Time domain chopping techniques combined with VCO tuning were applied to PLLbased sensor to digital converters to address the effect of dynamic offsets in [12][13][14]. The VCO tuning technique is aimed at reducing the residual offset after the chopping process.…”

Section: Introductionmentioning

confidence: 99%

Frequency-Based Sensor Interface with Dynamic Offset Compensation

et al. 2023

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Sensor interfaces need to be robust and accurate for many applications. This is more challenging for sensor systems operating in radiation environments because the mismatch between components grows as a result of the absorbed total ionizing dose (TID). In frequency-based sensor interfaces, the frequency drift of the voltage-controlled oscillator (VCO) can create dynamic output offset, gain, and linearity errors unless a calibration algorithm is included. In this paper, a digital intensive dynamic offset cancelation technique is proposed for an open loop VCO-based sensor to digital converter, which is achieved by making periodic adjustments to the average center biasing voltage of one of the VCOs in a differential architecture, in effect to make their center frequencies match. A simulation of the behavioral model of the proposed architecture was developed and hardware implementation of the whole system was performed on an FPGA by emulating, with digital modules, the characteristics of the two VCO outputs modulated with differential inputs. The results showed that the output offset error was reduced from around 5% to 0.1% for a relative oscillators’ drift close to 10% of the tuning range, and the SNDR is relatively maintained when subjected to variable relative VCO drifts.

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Modeling and Analysis of Drift-Cancellation Techniques for Time-Based Integrated Resistive Sensor Interfaces

Cited by 4 publications

References 20 publications

Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology

Frequency-Based Sensor Interface with Dynamic Offset Compensation

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