Modeling methodology of high-voltage substrate minority and majority carrier injections

Conte, Fabrizio Lo; Sallèse, Jean-Michel; Kayal, Maher

doi:10.1109/essderc.2010.5618395

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…Compact substrate model has been proposed in order to take into account the minority carriers propagation in circuit simulation [5]. The substrate model consists of special EPFL devices called EPFL diode, EPFL resistor and EPFL homojunction.…”

Section: Compact Substrate Modelmentioning

confidence: 99%

A CAD integrated solution of substrate modeling for industrial IC design

Zeng

Moursy

Iskander

et al. 2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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Smart Power IC integrating high voltage devices with low voltage control blocks becomes more and more popular in automotive industry recently. Minority carriers injected into the substrate during switching of high power stages cause malfunction of sensitive nearby low voltage devices. Sometimes this may be destructive due to the presence of triggered latch up. The minority carriers propagation is extremely hard to model and difficult to predict using existing commercial standard design flow. In this paper, we propose a Computer-Aided-Design solution to characterise the substrate vertical and lateral parasitic for Smart Power IC in automotive applications. Investigation of complex benchmark structures is presented. SPICE simulations are performed for extracted 3D substrate netlist and compared to measurements. Good fitting between simulation and measurement validates the effectiveness and accuracy of the proposed CAD tool.

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Section: Compact Substrate Modelmentioning

confidence: 99%

A CAD integrated solution of substrate modeling for industrial IC design

Zeng

Moursy

Iskander

et al. 2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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“…This solution reduces the simulation time when compared to TCAD. This new proposed methodology for substrate modeling relies on a network of interconnected diodes and resistances to represent the electrical substrate circuit [7]. A three-dimensional meshing strategy is necessary to extract from the circuit layout the equivalent substrate netlist.…”

Section: Introductionmentioning

confidence: 99%

Optimization strategy of numerical simulations applied to EPFL substrate model

Stefanucci

Buccella

Kayal

et al. 2014

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)

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A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit layout following a given substrate meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the influence of the meshing on the accuracy of the EPFL Substrate Model when compared to finite element simulations. A two-dimensional case study on a parasitic lateral bipolar is then proposed with both spice-like and finite element simulation results for the minority carriers diffusion. A linear model is developed to estimate the most important geometrical domains influencing the accuracy of the studied model.

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“…Minority carriers injection and propagation in substrate are the major causes of failure in smart power ICs. Hence, modeling the minority carriers is still necessary in high voltage applications [3]. A novel Computer-Aided-Design modeling methodology for substrate coupling-immune designs has been introduced in [4].…”

Section: Introductionmentioning

confidence: 99%

An adaptive mesh refinement strategy of substrate modeling for smart power ICs

Zeng

Moursy

Iskander

et al. 2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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Substrate noise coupling due to minority carriers propagation in smart power integrated circuit becomes a critical issue specially for high voltage applications. Computer-Aided-Design modeling methodology for substrate parasitic-immune design was introduced. It is based on constructing a 3D substrate equivalent network. The substrate equivalent network consists of models of diodes and resistors that are capable of preserving the continuity of minority carriers. In this paper, an optimized meshing topology for substrate modeling is introduced. This meshing topology contributes significantly in the extracted component reduction and hence speeds up the simulation while improving the convergence of the simulator. A typical NPN bipolar transistor is used as case study. Comparing the proposed meshing topology to the basic meshing topology, the number of extracted components is reduced by 78% and the simulation time is lowered by 88%. SPICE-like analysis results confirm the accuracy of modeling approach with an acceptable relevant error (<10%) compared to standard model. With the proposed meshing topology, it is feasible to model the substrate parasitic of more complex smart power integrated circuit.

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Modeling methodology of high-voltage substrate minority and majority carrier injections

Cited by 8 publications

References 6 publications

A CAD integrated solution of substrate modeling for industrial IC design

A CAD integrated solution of substrate modeling for industrial IC design

Optimization strategy of numerical simulations applied to EPFL substrate model

An adaptive mesh refinement strategy of substrate modeling for smart power ICs

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