Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

Zhang, Rui; Liu, Taizhi; Yang, Kexin; Milor, Linda

doi:10.1109/iirw.2017.8361243

Cited by 6 publications

(2 citation statements)

References 19 publications

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“…Although technology scaling enables integrated circuits (ICs) with higher density and better performance, it is still faced with serious vulnerability to various aging mechanisms appearing from front-end to back-end [1][2][3][4][5][6][7][8][9][10]. These aging mechanisms include Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Random Telegraph Noise (RTN), Gate-Oxide Breakdown (GOBD) at the front-end, Middle-of-line (MOL) time-dependent dielectric breakdown (TDDB), Back-end-of-line (BEOL) TDDB, and Electromigration (EM).…”

Section: Introductionmentioning

confidence: 99%

“…Such a degradation is expected to get even worse with further technology scaling. It is reported by ITRS-2015 that the operating current density has exceeded 1 MA/cm 2 and is rapidly approaching to 10 MA/cm 2 . Figure 1a shows the experiment and model Micromachines 2022, 13, 883 2 of 31 of lifetime scaling versus interconnect geometry, where an effective scaling model has been established by assuming the void is located at the cathode end of the interconnect which contains a single via with drift velocity dominated by interfacial diffusion [31].…”

Section: Introductionmentioning

confidence: 99%

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Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

2022

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The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.

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