Modelling parallel SiC MOSFETs: thermal self‐stabilisation vs. switching imbalances

Bertelshofer, Teresa; März, Andreas; Bakran, Mark-M.

doi:10.1049/iet-pel.2018.5418

Cited by 17 publications

(6 citation statements)

References 16 publications

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“…Based on the coupled inductance equivalent model established above, the output current change rate of the converter flux mutual aid and flux cancellation coupled inductance is expressed by Equations ( 18) and (19).…”

Section: The Operational Principle Of the Coupled Inductancementioning

confidence: 99%

“…Many studies have been performed on the imbalance of current suppression. From the view of the study object, the imbalance current suppression method can be classified into three categories: device classification; device operating condition monitoring; and circuit topology [14][15][16][17][18][19]. The chip screening method is proposed to solve the mismatch introduced by the asymmetric layout [20].…”

Section: Introductionmentioning

confidence: 99%

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A Magnetic Integration Mismatch Suppression Strategy for Parallel SiC Power Devices Applications

Sun,

Liu,

Chen

et al. 2024

Electronics

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A new magnetic integrated parallel current sharing control method for parallel silicon carbide (SiC) power devices is presented in this article. The problem of the application of parallel connected SiC power devices is analyzed. The coupled inductance method is adopted to solve the problem. Based on the active-back converter, we establish the theoretical model of the coupled inductance, and figure out its working mechanism. The integrated magnetic device is designed based on the working mechanism, and the effectiveness is determined through simulation. A 12 V/10 A output magnetic integrated active-flyback converter prototype is fabricated and tested to verify the strategy. Measurement results show that, with the proposed magnetic integrated method, the mismatch voltage is suppressed to 0.1 V under all load conditions, and the efficiency increases by at most 6.52% under full load conditions.

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Section: The Operational Principle Of the Coupled Inductancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Magnetic Integration Mismatch Suppression Strategy for Parallel SiC Power Devices Applications

Sun,

Liu,

Chen

et al. 2024

Electronics

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show abstract

“…However, manufacturers still have to use relatively small die sizes to achieve reasonable product yields [7]. Thus, despite the superior properties of SiC as a base material, in practice SiC MOSFETs must be parallelised to achieve the current levels demanded [8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…In addition, it is much harder to grow silica on SiC than on silicon substrates [14]. This poses a substantial challenge for the fabrication of MOS structures and results in, for example, a wider than desirable dispersion of threshold voltages among different devices of the same model [11,15,16]. Therefore, effective switching synchronisation is crucial for reliable parallelisation of SiC MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Multiple current amplifier‐based gate driving for parallel operation of discrete SiC MOSFETs

Aretxabaleta

Alegría

Gárate

et al. 2022

IET Power Electronics

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The shorter switching times of silicon carbide (SiC) MOSFETs enable power converters to operate at higher frequencies than with silicon IGBTs. However, because SiC MOSFET die sizes are still relatively small, several devices have to be connected in parallel to cope with the high current ratings demanded. For the total current to be evenly distributed among all the MOSFETs, the gate circuit and power layout must meet stringent symmetry requirements. However, space limitations on the circuit surface hinders the achievement of full symmetries on both the power and gate layouts because they constrain one another. This paper proposes a solution for safely paralleling discrete SiC MOSFETs while decoupling the gate and power layout designs. It requires placing one BJT-based fast current amplifier as close as possible to each MOSFET rather than using just one to feed all the MOS gates. This reduces the noise in the received gating signals and, more importantly, reduces the sensitivity of driver-gate path geometric / electric mismatches. This makes it possible to safely relax the symmetry requirements for the gating circuitry, thereby providing designers with more freedom to achieve better symmetry in the power layout.

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“…Generally, three approaches are considered to solve the imbalance current sharing problem in literatures [6][7][8][9][10][11][12][13][14][15][16][17][18]. In [6][7][8], authors try to present a manufacturing approach to produce MOSFET devices with the same parameters. However, this approach is rather hard and costly.…”

Section: Introductionmentioning

confidence: 99%

A passive compensator for imbalances in current sharing of parallel‐siC MOSFETs based on planar transformer

Sarfejo

Allahyari

Bahrami

et al. 2021

IET Power Electronics

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SiCMOSFETs are widely employed in power converters due to their high switching speed and low switching loss. However, their low current rating due to the limited active area restricts their high power applications. To apply SiC MOSFETs in high power applications, providing parallel connection is an inevitable choice. To tackle the challenge of imbalanced current sharing problem between parallel SiC MOSFETs, a new passive compensator based on planar transformer (PT) is proposed here. Compared with the conventional transformer compensators, parasitic elements are adjustable and predictable in PT compensators, which is especially important for mass production aims. After explaining the concept of the physical operation of the PT compensator, the whole parasitic elements of the PT compensator are formulated. Based on estimated parasitic elements and using the finite element method (FEM), an optimum PT structure is extracted for imbalances in current sharing of parallel SiC MOSFETs. Afterward, the PT design is discussed in detail and then, a boost converter is constructed. Finally, the experimental results are presented to verify the reliability, accuracy, and effectiveness of the theoretical results.

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Modelling parallel SiC MOSFETs: thermal self‐stabilisation vs. switching imbalances

Cited by 17 publications

References 16 publications

A Magnetic Integration Mismatch Suppression Strategy for Parallel SiC Power Devices Applications

A Magnetic Integration Mismatch Suppression Strategy for Parallel SiC Power Devices Applications

Multiple current amplifier‐based gate driving for parallel operation of discrete SiC MOSFETs

A passive compensator for imbalances in current sharing of parallel‐siC MOSFETs based on planar transformer

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