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This article presents a numerical method in combination with a device simulation model used to analyse the parallel connection of several silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) dies. Parallel connection is necessary to achieve the desired current carrying capability of the main inverters for xEV-drives. With this method, the effect of asymmetries within the chips' parameters, especially the gate threshold voltage, is investigated. The investigation results quantify to what extent the positive temperature coefficient of the on-state resistance can mitigate the overheating of one chip caused by switching loss imbalance. The results are used to define the necessary derating of the inverter output power so that no single chip is thermally overstressed.

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