Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Abstract

Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

Device overlay root cause process detection using patterned wafer geometry information

“…As the manufacturing process continues, stacked films with different levels of non-uniform residual stress induce overlay error, which we call process-induced overlay error. In many papers, process-induced overlay error has always been emphasized as a critical issue in OPO control [1,3,4,5]. Particularly, process-induced overlay errors in 3D NAND devices appear as the number of stacked layers increases accompanying non-uniform residual stress [6].…”

“…The PWG tool is suitable for high-volume manufacturing (HVM) process monitoring due to its high throughput for inline measurements that drive timely process corrections. There have been previous publications describing process-induced overlay error with PWG data-based metrics and applications to monitor and control OPO [5,7,8,1,3,9,4,10]. In-plane distortion (IPD) is a representative metric that estimates process-induced overlay errors.…”