Monolithic 2.5kV RMS, 1.8V&amp;#x2013;3.3V dual-channel 640Mbps digital isolator in 0.5&amp;#x03BC;m SOS

Moghe, Y.; A, Terry; Luzon, Dennis

doi:10.1109/soi.2012.6404389

Cited by 11 publications

(8 citation statements)

References 5 publications

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“…Experimental measurements were carried out at 3.3-V voltage supply up to a data rate of 40 Mbit/s and confirmed the simulated performance. (5) 3.8/0.9 (6) Assembling/Package Standard Stacked chips with DAF (7) Standard Standard Standard…”

Section: Resultsmentioning

confidence: 99%

“…An integrated galvanic barrier can be implemented by using silicon dioxide (SiO 2 ), which exhibits a breakdown voltage (BV) of about 1000 V/µm [3], sometimes in combination with silicon nitride (Si 3 N 4 ) and oxynitride (SiON) to further improve its isolation rating [4]. Oxide galvanic isolation has been successfully exploited in recent years for highly integrated isolated data [5][6][7] and power transfer interfaces [8][9][10][11][12] by means of on-chip capacitors or stacked transformers. However, oxide insulation can reliably provide a limited surge capability (typically 5-6 kV), since increasing the oxide thickness produces wafer mechanical stress and second order BV effects.…”

Section: Technologies For Chip-scale Galvanic Isolatorsmentioning

confidence: 99%

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A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

et al. 2020

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This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs.

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Section: Resultsmentioning

confidence: 99%

Section: Technologies For Chip-scale Galvanic Isolatorsmentioning

confidence: 99%

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

et al. 2020

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“…Signal is transmitted from low-side to high-side by coupling since there is no direct connection between those two sides. Inductively coupled isolation methods provide the isolation through on-chip micro-transformers [2,3,4,5,6,7,8], and capacitive-coupled isolation methods utilize on-chip SiO2 capacitor as isolation barrier [9,10,11,12]. More work and research were done in these methods.…”

Section: Introductionmentioning

confidence: 99%

A dV/dt noise canceling circuit of capacitive-isolated gate drivers

Zhang

Liu

Quan

et al. 2022

IEICE Electron. Express

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For capacitive-isolated gate drivers, the pulse width distortion (PWD) and common mode transient immunity (CMTI) are vital factors to evaluate its performance. In this paper, an envelope detection circuit and a dV/dt noise canceling circuit of capacitive-isolated gate drivers is designed based on X-FAB 0.35μm CMOS process. With these structures, this gate driver alleviates PWD and improve CMTI. Spectre simulation results show that the gate driver achieves 200kV/μs CMTI with 50ns propagation delay and maximum 7.4ns PWD. Besides, it has better robustness to fabrication process and temperature variation than conventional methods.

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“…Digital isolators fabricated in complementary metallic oxide semiconductor (CMOS) process technology are gaining favor from designers because of their significant advantages in terms of speed (100-150 Mbps), power dissipation, propagation delays, and more [3,4] . Digital isolators using magnetic coupling [5][6][7] , capacitive coupling [8,9] and giant magneto resistive (GMR) [10] methods have been reported in the academic literature and commercially. They are challenging the optocouplers.…”

Section: Introductionmentioning

confidence: 99%

4-port digital isolator based on on-chip transformer

et al. 2018

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The design and fabrication results of a 4-port digital isolator based on an on-chip transformer for galvanic isolation are presented. An ON–OFF keying modulation scheme is used to transmit the digital signal. The proposed digital isolator is fabricated by the 0.18 μm CMOS process. A test chip can achieve a 1 MHz signal bandwidth, a 40 ns propagation delay, a 35.5 mW input power and a 50 mA drive output current. The proposed digital isolator is pin-compatible, of small volume and low power replacement for the common 4-port optocoupler.

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Monolithic 2.5kV RMS, 1.8V–3.3V dual-channel 640Mbps digital isolator in 0.5μm SOS

Cited by 11 publications

References 5 publications

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

A dV/dt noise canceling circuit of capacitive-isolated gate drivers

4-port digital isolator based on on-chip transformer

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