Monolithic CMOS-compatible AlGaInP visible LED arrays on silicon on lattice-engineered substrates (SOLES)

Chilukuri, Kamesh; Mori, M.; Dohrman, Carl L.; Fitzgerald, Eugene A.

doi:10.1088/0268-1242/22/2/006

Cited by 70 publications

(39 citation statements)

References 9 publications

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“…DMZn and DETe were used for p-and n-type doping. The p-type doping concentration was targeted at 5×10 17 /cm 3 and n-type at 2×10 18 /cm 3 . The thicknesses of p-InAlP, i-InGaP, and n-InAlP are 500 nm, 300 nm, and 300 nm, respectively.…”

Section: Methodsmentioning

confidence: 99%

“…Therefore it is still important to develop AlGaInP LEDs on Si substrates to cover the red and yellow-green wavelength range. AlGaInP LEDs are usually grown on lattice-matched GaAs substrates and to bridge the lattice-mismatch with Si, buffer layers have to be inserted between the III-V LED and Si substrate 3 . Ge is a good candidate as the buffer.…”

Section: Introductionmentioning

confidence: 99%

“…AGaInP LED arrays have been demonstrated on engineered Ge/GeSi substrate and integrated with CMOS 3 . Due to the thick Ge/GeSi buffer, the integration scheme is still complicated 3 . It is therefore desirable to develop InGaP LEDs on direct grown Ge-on-Si substrate without the thick compositional-graded GeSi buffers.…”

Section: Introductionmentioning

confidence: 99%

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Red InGaP light-emitting diodes epitaxially grown on engineered Ge-on-Si substrates

et al. 2016

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The integration of light emitting devices on silicon substrates has attracted intensive research for many years. In contrast to the InGaN light emitting diodes (LEDs) whose epitaxy technology on Si substrates is robust and mature, the epitaxy of other compound semiconductor light emitting materials covering the visible wavelength range on Si is still challenging. We have studied epitaxial growth of red InGaP light emitting materials on engineered Ge-on-Si substrates. Ge-on-Si was grown on 8'' Si substrates in a metal organic chemical vapour deposition (MOCVD) reactor using twostep growth and cycling annealing. Threading dislocation densities (TDDs) were controlled to as low as 10 6 /cm 2 by using As-doped Ge initiation. A GaAs buffer layer and lattice-matched InGaP LEDs were grown on the Ge-on-Si sequentially in the same MOCVD process and red LEDs are demonstrated. InGaP multiple-quantum-well LED structures were grown on full 8'' Ge-on-Si substrates and characterized.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Red InGaP light-emitting diodes epitaxially grown on engineered Ge-on-Si substrates

et al. 2016

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“…As an example, we report the integration of InGaP light-emitting diodes (LEDs) with silicon CMOS. InGaP red LEDs are commercially available for about two decades and the integration with CMOS was explored previously [2,3]. Nowadays InGaP LEDs have various applications such as lighting, display, sensing, etc.…”

Section: Introductionmentioning

confidence: 99%

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

et al. 2017

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“…The ρ c for these NiSi/Si interfaces (with n-type ion-implanted Si and epitaxially-grown n+ and p+ Si on undoped GaAs) are shown in Figure 11a. All NiSi/Si interfaces have ρ c below 1e-6 -cm 2 . Since doping concentrations in all samples are between 1-2e20 cm −3 , even better ρ c might be expected with further improvements via a more established industrial fabrication process.…”

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confidence: 98%

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Pacella

Mukherjee

Bulsara

et al. 2013

ECS J. Solid State Sci. Technol.

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Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar integration of III-V and Si CMOS devices in a common fabrication infrastructure. A method of making ohmic contacts to buried III-V films using silicide metallurgies has been established. NiSi/Si/III-V dual heterojunction contact structures are found to be optimal for integration. These structures allow contact resistivities to be controlled by Si/III-V interfaces and eliminate interactions between the buried III-V device and metal layers. Using a modified transmission line method (TLM) test structure fabricated using standard CMOS processing techniques, the specific contact resistivities of Si/GaAs and Si/In x Ga 1-x As interfaces are extracted. The relationship between specific contact resistivity and heterojuntion barrier width is considered. Among the structures tested in this work, p-type Si/GaAs and n-type Si/In x Ga 1-x As yielded the lowest contact resistivities. Using the p-type Si/GaAs interface, a GaAs/Al x Ga 1-x As laser with NiSi top contact is demonstrated, confirming the feasibility of NiSi/Si/III-V contact structures for III-V devices. Integration of III-V compound (III-V) semiconductors with Si complementary metal-oxide semiconductor (CMOS) has been an area of great interest because of the circuit performance enhancement that can be gained by placing Si and III-V devices in close spatial proximity. The Silicon-on-Lattice-Engineered Substrate (SOLES) platform enables this integration monolithically. The SOLES wafer is a silicon wafer with an embedded template suitable for epitaxial III-V device growth.1-3 CMOS devices are fabricated on the surface silicon and III-V devices are built on the template layer in windows. In collaboration with other groups, we have successfully demonstrated differential amplifiers with InP heterojunction bipolar transistors (HBT) and Si CMOS devices on SOLES substrates. 4 In this previous work, Si and III-V contact metallization steps were performed separately in traditional CMOS and III-V infrastructure, respectively. We envision parallel metallization of the CMOS and III-V devices using common CMOS infrastructure, in a manner consistent with Si processing, as a final step toward ultimate monolithic integration.A few key requirements must be considered in choosing the optimal contact structure. Contacting the III-V films through a Si encapsulation layer which fully embeds the III-V device and minimizes exposure of III-V materials to the CMOS sequence will cause the least disruption to CMOS processes. This Si may be grown in an epitaxial step that is integrated with III-V device growth, streamlining the growth process.Using CMOS-friendly metals and processing steps which parallel those currently found in CMOS processing will also ease the integration. This metal must have a thermal budget of formation that is low to minimize effects on the III-V devic...

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Monolithic CMOS-compatible AlGaInP visible LED arrays on silicon on lattice-engineered substrates (SOLES)

Cited by 70 publications

References 9 publications

Red InGaP light-emitting diodes epitaxially grown on engineered Ge-on-Si substrates

Red InGaP light-emitting diodes epitaxially grown on engineered Ge-on-Si substrates

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

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