MOS Current Mode Logic Near Threshold Circuits

Abstract

Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

“…1) operates in the saturation region, the PDPs and EDPs of the hybrid-CMOS adder are higher in comparison to the MCML full adder. This is in accordance with the simulation results obtained and those mentioned in (Shapiro and Friedman 2014). In addition, for more energy efficient designs the use of very low voltage swing is recommended since the MCML full adder does not possess a theoretical…”

“…In addition to higher speed, the MCML full adder generates an insignificant amount of simultaneous switching (SS) noise because it is operated with a constant bias current unlike its hybrid CMOS counterpart (Shapiro and Friedman 2014). Moreover, the SS noise generated is independent of the switching state (i.e.…”

Design of Filter Using MOS Current Mode Logic

“…MCML ring oscillator consumes less power. Static power dissipation of the circuit is reduced because of its low voltage [9]. This paper addresses the design of filter using MCML logic.…”

Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz

“…A logic family that uses differential inputs and outputs is MOS Current Mode Logic (MCML) and the logic gated from this family is the NAND gate. The MCML family has other advantages such as much stronger noise immunity, no switching power consumption because it's a current steering logic family and better energy usage at high frequencies [11,12]. The drawbacks of MCML is that it needs biasing circuitry which requires more hardware and more complicated equivalent models.…”